• Discussion

  How to make SoC Encounter export Verilog with added VDD/VSS pins Locked

  1969 views
  2 replies
  Latest over 15 years ago
  by Vishnu Chada
• Discussion

  Delay Line Model Locked

  13883 views
  0 replies
  Started over 15 years ago
  by pitter
• Discussion

  implement GAIN as a parameter Locked

  13147 views
  3 replies
  Latest over 15 years ago
  by oldmouldy
• Discussion

  CDF callbacks and ADE design variables? Locked

  14697 views
  1 reply
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  StrmOut from Virtual Memory Locked

  20983 views
  13 replies
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  Missing drill symbols in ART work Locked

  16221 views
  3 replies
  Latest over 15 years ago
  by archive
• Discussion

  Fab Drawing Issue Locked

  15736 views
  5 replies
  Latest over 15 years ago
  by archive
• Discussion

  Hole symbols from mirrored symbol pins not showing on Fab Layer Gerber Locked

  17507 views
  7 replies
  Latest over 15 years ago
  by archive
• Discussion

  overlap of metals Locked

  15907 views
  5 replies
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  Adding tie low cells on only requried pins Locked

  13541 views
  0 replies
  Started over 15 years ago
  by KVBABU
• Discussion

  second event must occur in TCM Locked

  13109 views
  0 replies
  Started over 15 years ago
  by iriss
• Discussion

  fanning out to a copper shape on board bottom Locked

  13024 views
  1 reply
  Latest over 15 years ago
  by oldmouldy
• Discussion

  autorouting on a layer with a copper shape Locked

  12853 views
  1 reply
  Latest over 15 years ago
  by redwire
• Discussion

  problem with mmsim61 Locked

  16036 views
  6 replies
  Latest over 15 years ago
  by Tawna
• Discussion

  How target nets in a relative delay group are determined in the specctra autorouter? Locked

  14836 views
  1 reply
  Latest over 15 years ago
  by tomoo