• Discussion

  Max tran violations Locked

  21191 views
  5 replies
  Latest over 16 years ago
  by frankz
• Discussion

  CTS in nanometer design Locked

  13916 views
  2 replies
  Latest over 16 years ago
  by frankz
• Discussion

  clock tree quality Locked

  18584 views
  10 replies
  Latest over 16 years ago
  by frankz
• Discussion

  Why do we go for virtual clocks?? Locked

  18424 views
  7 replies
  Latest over 16 years ago
  by frankz
• Discussion

  ncvlog: *E,RIMPCD: error reading implicit cds.lib Locked

  2829 views
  4 replies
  Latest over 16 years ago
  by AshVarma
• Discussion

  Metal layer constraining Locked

  13884 views
  2 replies
  Latest over 16 years ago
  by NAADHAN
• Discussion

  Cadence IC 6.1.3 Simualtion Locked

  7727 views
  9 replies
  Latest over 16 years ago
  by StreamCX
• Discussion

  Internal Error on IUS8.2-b003 Locked

  13702 views
  1 reply
  Latest over 16 years ago
  by StephenH
• Discussion

  can lay out engineer change the width of a resistor? Locked

  14943 views
  4 replies
  Latest over 16 years ago
  by Andrew Beckett
• Discussion

  Replay of Script

  14074 views
  2 replies
  Latest over 16 years ago
  by Jmac0585
• Discussion

  Auto-Router Clearence Conflicts Locked

  12778 views
  0 replies
  Started over 16 years ago
  by PherricOxide
• Discussion

  Setting "schematic" as stop view in Spectre netlister Locked

  3254 views
  2 replies
  Latest over 16 years ago
  by hkutuk
• Discussion

  Importing a Mentor Neutral File into Allegro??? Locked

  17736 views
  7 replies
  Latest over 16 years ago
  by AcAe
• Discussion

  SKILL equivalent for MOD function

  18105 views
  1 reply
  Latest over 16 years ago
  by Nagaraj Shanmu
• Discussion

  Setting of Constraint region... Locked

  16478 views
  6 replies
  Latest over 16 years ago
  by Ejlersen