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Discussion

Profiling the runtime of SystemVerilog Assertions Locked

17922 views

4 replies

Latest over 16 years ago
by danlarkin
Discussion

Temporal expression in e Locked

14878 views

5 replies

Latest over 16 years ago
by mstellfox
Discussion

Importing CSI capture schematic to PCB Editor Locked

15314 views

4 replies

Latest over 16 years ago
by Ejlersen
Discussion

Board Dimension with Japanese Character Locked

19655 views

15 replies

Latest over 16 years ago
by purikku22
Discussion

ddDeleteObj doesn't work in nograph mode Locked

2860 views

5 replies

Latest over 16 years ago
by skillUser
Discussion

cannot run simvision Locked

14911 views

1 reply

Latest over 16 years ago
by Mickey
Discussion

Problem with tutorial - Repeated part IDs in Hierarchical tutorial Locked

2304 views

2 replies

Latest over 16 years ago
by scotty2541
Discussion

OrCAD Capture DEMO - Tutorial disconnect from actual program Locked

1286 views

2 replies

Latest over 16 years ago
by scotty2541
Discussion

How to preserve logical function at hierarchical ports after some timing optimizations done with setOptMode -preserveModuleFunction false. Locked

1145 views

0 replies

Started over 16 years ago
by dlferrao
Discussion

16.2 - Can't change impedance value in cross section Locked

3881 views

9 replies

Latest over 16 years ago
by redwire
Discussion

How can I do in do files to match the length of differential pairs? Locked

12780 views

0 replies

Started over 16 years ago
by hg527
Discussion

Allegro v15.2 Locked

13135 views

1 reply

Latest over 16 years ago
by Prasanna
Discussion

how to set TMP directories in IUS6 Locked

14065 views

1 reply

Latest over 16 years ago
by Bernd
Discussion

AXI EVC user manual Locked

14378 views

1 reply

Latest over 16 years ago
by StephenH
Discussion

well tap and End cap cells Locked

13795 views

0 replies

Started over 16 years ago
by gops