• Discussion

  adding fillets in 16.01 Locked

  12609 views
  0 replies
  Started over 16 years ago
  by wolf
• Discussion

  Duplicate emails (was: RE: 16.2 - Can't change impedance value in cross section) Locked

  332 views
  0 replies
  Started over 16 years ago
  by AndyG
• Discussion

  MOS cap configurations and calculation Locked

  13624 views
  0 replies
  Started over 16 years ago
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• Discussion

  Reuse package symbols (*.dra) in OrCAD Layout ? Locked

  13111 views
  1 reply
  Latest over 16 years ago
  by redwire
• Discussion

  Is it possible to change padstack characteristics inside a PCB

  13866 views
  4 replies
  Latest over 16 years ago
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• Discussion

  Trigger on Select/Unselect Locked

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  8 replies
  Latest over 16 years ago
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• Discussion

  How do you take the cdr of a tconc list? Locked

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  2 replies
  Latest over 16 years ago
  by dmay
• Discussion

  axlDBCreatePath

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  4 replies
  Latest over 16 years ago
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• Discussion

  Layout Instance Names on VNL Netlists? Locked

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  1 reply
  Latest over 16 years ago
  by tpylant
• Discussion

  Reminder: Encounter Digital Implementation Office Hours Starting Soon Locked

  13293 views
  0 replies
  Started over 16 years ago
  by BobD
• Discussion

  can LEC provide cdc check? Locked

  19207 views
  9 replies
  Latest over 16 years ago
  by timmynolan
• Discussion

  adding simulator views to a PDK (additional questions) Locked

  13351 views
  0 replies
  Started over 16 years ago
  by Aksl
• Discussion

  Op- Amp loop gain measurement Locked

  1513 views
  1 reply
  Latest over 16 years ago
  by johannes
• Discussion

  Verilog-XL install Locked

  14137 views
  0 replies
  Started over 16 years ago
  by bdatta
• Discussion

  What different between PCB Editor15.5 and PCB Editor16.0

  13505 views
  2 replies
  Latest over 16 years ago
  by ELEKVN