• Discussion

  what is the link to download older version of IUS? Thanks Locked

  14349 views
  1 reply
  Latest over 16 years ago
  by aplumb
• Discussion

  PCB Design with FPGA (TQFP or BGA package) Locked

  14677 views
  3 replies
  Latest over 16 years ago
  by nramesh2244
• Discussion

  Help needed on Allegro SI tool (V15.5) Locked

  13009 views
  1 reply
  Latest over 16 years ago
  by redwire
• Discussion

  d_cellview Locked

  15273 views
  4 replies
  Latest over 16 years ago
  by ahamlett
• Discussion

  relay Locked

  13247 views
  0 replies
  Started over 16 years ago
  by JETEE
• Discussion

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  16927 views
  2 replies
  Latest over 16 years ago
  by kerchunk
• Discussion

  Simulting Layout synthesized with SOC Encounter Locked

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  1 reply
  Latest over 16 years ago
  by Sirrius
• Discussion

  SOC Encounter: Problem with multiple clocks Locked

  14294 views
  2 replies
  Latest over 16 years ago
  by Sirrius
• Discussion

  SOC Encounter: Problem with multiple clocks Locked

  13841 views
  1 reply
  Latest over 17 years ago
  by BobD
• Discussion

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  13437 views
  1 reply
  Latest over 17 years ago
  by BobD
• Discussion

  clock nets routing Locked

  14346 views
  1 reply
  Latest over 17 years ago
  by BobD
• Discussion

  Load ADE state from skill Locked

  15150 views
  3 replies
  Latest over 17 years ago
  by jtompson
• Discussion

  PDF write

  15724 views
  6 replies
  Latest over 17 years ago
  by satya12
• Discussion

  How impidennce related to trace width /spacing.

  13441 views
  1 reply
  Latest over 17 years ago
  by satya12
• Discussion

  Keep text attachment with symbol

  14215 views
  3 replies
  Latest over 17 years ago
  by satya12