• Not Answered

  How to fix this error when I trying to export the ODB++ in allegro. 0

  8441 views
  3 replies
  Latest over 2 years ago
  by jc teyssier
• Discussion

  How to manage the line width of dimensions?

  7529 views
  3 replies
  Latest over 2 years ago
  by masamasa
• Discussion

  Using Ocean Script in cross corner simulation in Assembler Locked

  7129 views
  1 reply
  Latest over 2 years ago
  by ShawnLogan
• Discussion

  Optimizing Interaction: Using Scripting for Enhanced Functionality on Dumps4free

  3513 views
  0 replies
  Started over 2 years ago
  by Broden Ellington
• Discussion

  Why cannot I see connection lines in the layout?

  6954 views
  1 reply
  Latest over 2 years ago
  by Broden Ellington
• Answered

  Copying one part to project library copies whole library +1

  3646 views
  2 replies
  Latest over 2 years ago
  by further
• Discussion

  RLC S-Parameter Analysis vs Clarity 3D Inductance-Capacitance Extraction Results Comparison Locked

  6108 views
  1 reply
  Latest over 2 years ago
  by Andrew Beckett
• Not Answered

  Generic symbols 0

  3948 views
  1 reply
  Latest over 2 years ago
  by rg13
• Discussion

  AMS simulation IE settings Locked

  11188 views
  5 replies
  Latest over 2 years ago
  by paulinho
• Discussion

  simultaneous simulation of extracted and schematic views? Locked

  6308 views
  2 replies
  Latest over 2 years ago
  by hesaliveJim
• Answered

  Best Practices - Defining and placing jumpers with arbitrary distance ? 0

  2598 views
  4 replies
  Latest over 2 years ago
  by John T
• Answered

  Adding custom anti-pad for Backdrill in the adjacent layer 0

  8045 views
  5 replies
  Latest over 2 years ago
  by John T
• Answered

  Size of the geometry different from what is shown in the demo video 0

  2338 views
  1 reply
  Latest over 2 years ago
  by Colinda
• Not Answered

  How do you use allegro_uprev to update .dra padstacks, etc.? I need to update my library, and using DBdoctor is a little tedious. 0

  6931 views
  1 reply
  Latest over 2 years ago
  by oldmouldy
• Discussion

  How to make sure Genus does not insert buffers with on/off VDD in a signal's network? Locked

  956 views
  0 replies
  Started over 2 years ago
  by 2tojohny