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  • Discussion

    Saving Internal Junction Temperature of VBIC Bipolar Transistor Model Locked

    8098 views
    5 replies
    Latest over 2 years ago
    by sgcad
  • Suggested Answer

    skill for check symbols outline overlapping 0

    6831 views
    2 replies
    Latest over 2 years ago
    by ivy372
  • Discussion

    IC20 Rulers/Measurement Question Locked

    1773 views
    2 replies
    Latest over 2 years ago
    by Andrew Beckett
  • Suggested Answer

    3D View: Via shows it is covered with Dynamic Copper 0

    6286 views
    1 reply
    Latest over 2 years ago
    by John T
  • Discussion

    hiCreateWindow, hiSetViewfile and html files Locked

    6003 views
    2 replies
    Latest over 2 years ago
    by Aldo3
  • Not Answered

    Schematic symbol library file is locked by a design and not released after closing capture 0

    6564 views
    4 replies
    Latest over 2 years ago
    by Jim OMahony
  • Discussion

    Hyperlink to open a cellView Locked

    6062 views
    2 replies
    Latest over 2 years ago
    by Aldo3
  • Suggested Answer

    odb++ import 0

    16002 views
    5 replies
    Latest over 2 years ago
    by masamasa
  • Answered

    Mapping a STEP-file to a footprint (symbol) breaks the CIS explorer footprint preview when using a local database... 0

    6734 views
    6 replies
    Latest over 2 years ago
    by Ulf K
  • Discussion

    How can I take a real value and assign it to a node in this case the output port of my module Locked

    6081 views
    2 replies
    Latest over 2 years ago
    by Wasif Absar
  • Discussion

    ADC Verification Workshop link is showing as retired,can I get this content, please Locked

    2006 views
    1 reply
    Latest over 2 years ago
    by Andrew Beckett
  • Discussion

    AOP Netlisting failed because of errors in callback Locked

    6162 views
    1 reply
    Latest over 2 years ago
    by Andrew Beckett
  • Suggested Answer

    OrCAD Tip of the week: Opening the DSN file directly from the file explorer is leading to PCB editor window and not the capture schematic 0

    10436 views
    1 reply
    Latest over 2 years ago
    by rg13
  • Discussion

    Compile and elaborate problem with VerilogA blocks in AMS simulation Locked

    6290 views
    0 replies
    Started over 2 years ago
    by zhaoyu
  • Suggested Answer

    axlDBCheck being obsoleted 0

    2717 views
    3 replies
    Latest over 2 years ago
    by DavidJHutchins
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