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Forum - Thread List
  • Discussion

    Getting the number of vertice on a CLINE

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    3 replies
    Latest over 18 years ago
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  • Discussion

    SV transaction sequence dependency constraint? Locked

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    5 replies
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  • Discussion

    Database corruption after rip up etch Locked

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    2 replies
    Latest over 18 years ago
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  • Discussion

    Dynamic copper fill problem Locked

    12755 views
    0 replies
    Started over 18 years ago
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  • Discussion

    Dynamic copper fill problem Locked

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    Started over 18 years ago
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  • Discussion

    Dynamic copper fill problem(?) Locked

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    Started over 18 years ago
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  • Discussion

    How to make nanoroute understand "USEMINSPACING" Locked

    6799 views
    4 replies
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  • Discussion

    15.7 constraint manager crashing Locked

    13125 views
    1 reply
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  • Discussion

    Export Possibilities for PCB Editor and Design Entry Locked

    14566 views
    5 replies
    Latest over 18 years ago
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  • Discussion

    PCAD to Allegro Locked

    18139 views
    8 replies
    Latest over 18 years ago
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  • Discussion

    Getting the techfile name

    12808 views
    0 replies
    Started over 18 years ago
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  • Discussion

    uRM task-level interface? Locked

    14339 views
    3 replies
    Latest over 18 years ago
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  • Discussion

    RTL Compiler: 1'b0/1'b1 instead of LOGIC0/LOGIC1 cells Locked

    1450 views
    1 reply
    Latest over 18 years ago
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  • Discussion

    compile SystemVerilog and Verilog separately? Locked

    19584 views
    8 replies
    Latest over 18 years ago
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  • Discussion

    axl function for parasitics?

    13776 views
    2 replies
    Latest over 18 years ago
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