• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    PCB Editor: Component value class not showing on render Locked

    11275 views
    0 replies
    Started over 4 years ago
    by eddoh
  • Discussion

    BB via's showing as Antenna via's Update to Respective layer

    3662 views
    0 replies
    Started over 4 years ago
    by wecan
  • Discussion

    OrCad CIS temperature field shows "°C" Locked

    1718 views
    1 reply
    Latest over 4 years ago
    by Yourigh
  • Discussion

    How can I get verilog-A code of RPI a-Si TFT model and RPI poly-Si TFT model? Locked

    16562 views
    7 replies
    Latest over 4 years ago
    by yysunj
  • Discussion

    Finding Pwr and Gnd sensitivity property of a pin Locked

    13336 views
    4 replies
    Latest over 4 years ago
    by DennisJ75
  • Discussion

    CAPTURE: NETLIST_IGNORE for hierarchical objects? Locked

    10858 views
    0 replies
    Started over 4 years ago
    by eddoh
  • Discussion

    Adding Pins to selected instance in schematic Locked

    16057 views
    6 replies
    Latest over 4 years ago
    by MicheleAncis
  • Discussion

    Add pins automatically in schematic Locked

    15776 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    a procedure to generate a binary waveform for plot Locked

    15495 views
    9 replies
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    Internally Connected Pins on Cell Layouts are Not Working Locked

    12781 views
    2 replies
    Latest over 4 years ago
    by Zeke KJ7NLL
  • Discussion

    Simulating 4 bit sequence in one simulation Locked

    15400 views
    4 replies
    Latest over 4 years ago
    by sidm
  • Discussion

    Capture CIS: how enable sort by converted value of a column Locked

    11137 views
    0 replies
    Started over 4 years ago
    by eddoh
  • Discussion

    BB via padstack value verification

    13545 views
    0 replies
    Started over 4 years ago
    by wecan
  • Discussion

    What is the best practice of optimize both CMRR PSRR and DC Gain of an amplifier? Locked

    15681 views
    6 replies
    Latest over 4 years ago
    by SimbaG
  • Discussion

    How to convert multiple Hatch shapes to solid conversion in Allegro?

    13371 views
    0 replies
    Started over 4 years ago
    by wecan
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information