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Problem in importing CDL/Spice netlist ...?

Hi! All,
Once again I need your help. I am using Cadence IC514 version.
I am trying to import a spice netlist using " CDL->Import " to make a corresponding schematic.
I am able to import MOS transistors successfully but not capacitors & resistors.
Here are the files that I am using for 'CDLIn' along with error output files ...
******************************

*******************************************************
FileName:- map.in
******************
devMap := nfet nch
termMap := D D G G S S B B
propMap := w w m simM
addProp := model nch

devMap := pfet pch
termMap := D D G G S S B B
propMap := w w m simM
addProp := model pch

devMap := capacitor nmoscap_25
termMap := PLUS PLUS MINUS MINUS
propMap := c c
addProp := model nmoscap_25

devMap := phyres rppolywo_m
termMap := PLUS PLUS MINUS MINUS SUB BULK
propMap := r res w sumW l sumL addProp := model rppolywo_m
*************************************************************************************
FileName:- test.sp
*******************
* SPICE NETLIST
***************************************
*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM

***************************************
.SUBCKT nmoscap_25 PLUS MINUS
.ENDS
***************************************
.SUBCKT rnpolywo_m PLUS MINUS BULK
.ENDS
***************************************
.SUBCKT test vss vdd out
** N=3 EP=3 IP=0 FDC=2
X0 out vss nmoscap_25 lr=1e-06 wr=1e-06 $X=13640 $Y=900 $D=286
X1 vdd out vss rppolywo_m lr=1e-05 wr=2e-06 $X=770 $Y=450 $D=370
.ENDS
*************************************************************************************
FileName:- ni.log
*************************
############################################
Reference Libraries...
basic
analogLib
tsmcN65
test_bt2
###################################
---- Device-mapping enabled ----
3 subckt(s) found in the netlist file.
==========================
Subckt: test
==========================
==========================
Subckt: nmoscap_25
==========================
Created the CV nmoscap_25->netlist_tmp.
ERROR (CDLIN-44): The sub-circuit 'nmoscap_25' does not have any instance (box element). Hence, its
schematic view will not be prepared.
Usage error.
TERED 0 ERRORS ( 5 WARNINGS) DURING FILE INPUT
FILE :./RUNS/test.sp
*** NUMBER OF ELEMENT BOXES DEFINED : 2
*************************************************************************************
FileName:- ni.err
**************************
PROCESSING INPUT FILE: ./RUNS/test.sp
*** WARNING : *.EQUATION IS NOT SUPPORTED BY CDLIN. IGNORED
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT nmoscap_25 ** WARNING ** BOX NAME CAN NOT START WITH B,C,D,M,P,R AND CAN HAVE THREE CHARACTERS ONLY
*/W* WARNING ***: NO ELEMENT INSIDE SUBCKT rnpolywo_m ** WARNING ** BOX NAME CAN NOT START WITH B,C,D,M,P,R AND CAN HAVE THREE CHARACTERS ONLY

FILE :./RUNS/test.sp
*** NUMBER OF ELEMENT BOXES DEFINED : 2
*************************************************************************************

I hope this information is apropos.
Please, Can someone guide me to resolve this issue.

Thanks in Advance ...

--
Prabhakar. K
IC Layout Engineer
SoCtronics Tech. Pvt. Ltd.
e-mail: prabhu.usic@gmail.com
---
(-: 'GOAL' : Perhaps there's more than one way to reach it :-)

Quek over 14 years ago

Hi Prabhakar

I think cdl-in should work if you make the following modifications to the netlist:

a. Remove the empty subckt definitions for the primitive devices
b. Change "X0" to "C0" and "X1" to "R1"

Best regards
Quek
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Prabhu The ICL over 14 years ago

Hi! Quek,
As you suggested I made the modifications to the
netlist. All is going fine except when there are 2-terminal & 3-termianl
resistors exist.
If I use the same prefix (i.e. R) for both the devices CDLIN translating
only 2-terminal device for both the statements.
I mean ... consider the following two statements ...

R0 vdd out vss rppolywo_m lr=1e-05 wr=2e-06 (==> 3-terminal res)
R1 net1 net2 rppolywo l=1e-05 w=2e-06 (==> 2-terminal res)

For the above two statements I am getting 'rppolywo' device.
In addition to this issue can you clear me for one more issue .. If you
don't mind ...!
How to translate different types of MOS devices ...?
Suppose, If I have pch, pch_mac, pch_25_mac etc .. devices which
corresponds to model 'nfet' , How to write map file in this case. I mean
how to
differentiate them with prop 'subType' ...?

--
Thanks & Regards
---
Prabhakar. K
IC Layout Engineer
SoCtronics Tech. Pvt. Ltd.
Hyderabad-INDIA
e-mail: prabhu.usic@gmail.com
-
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Quek over 14 years ago

Hi Prabhakar

Here is what you need to do:

a. Use a text editor to search and replace the different mos models (e.g. pch, pch_mac, etc) with 2 character models. E.g. PM, PV, etc. Cdl netlist in IC5141 uses the Dracula engine and only recognizes 2 character models.

devMap := pfet pch
propMatch := subtype PM
termMap := D D G G S S B B
propMap := w cdfW l cdfL

devMap := pfet pch_mac
propMatch := subtype PV
termMap := D D G G S S B B
propMap := w cdfW l cdfL

b. For 3 terminal resistors, please use the following device map. You need to use "phyres" category device type instead of "resistor".

devMap := phyres res3term
termMap := PLUS PLUS MINUS MINUS SUB SUB
propMatch := r 100
propMap := r r w w l l

Usually resistors in cdl netlist has a single value so you can use the "r" value to import the resistors.

Best regards
Quek
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Prabhu The ICL over 14 years ago

Hi! Quek,
I have succeeded in translating different type of MOS
devices as you described ...
But regarding resistors, I am keep getting the same issue ... In my case
resistors in cdl netlist doesn't contain 'r' value .. So I can't import
them using
'r' value ... I tried to match other properties but in vain ... Is there
any alternative to this ...
Please, consider the following cdl netlist & dev-map files for your
reference ...
************************************************************
*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM

.SUBCKT rppolywo_m PLUS MINUS BULK
.ENDS

.SUBCKT rppolywo PLUS MINUS
.ENDS

.SUBCKT nmoscap_25 PLUS MINUS
.ENDS

.SUBCKT test1 I Y gnd vdd
*.PININFO I:I gnd:I vdd:I Y:O
CC1 net022 gnd nmoscap_25 lr=1u wr=1u m=1
CC0 net024 gnd nmoscap_25 lr=1u wr=1u m=1
RR1 net9 net022 gnd rppolywo_m lr=20u wr=2u m=1 mf=1 mismatchflag=0
RR0 net5 net024 rppolywo l=10u w=2u m=1
MM5 net5 I gnd gnd NM l=60n w=200n m=1
MM4 net9 net5 gnd gnd NV l=60n w=200n m=1
MM3 Y net9 gnd gnd NH l=280n w=400n m=1
MM2 Y net9 vdd vdd PH l=280n w=400n m=1
MM1 net9 net5 vdd vdd PV l=60n w=200n m=1
MM0 net5 I vdd vdd PM l=60n w=200n m=1
.ENDS
************************************************************
devMap := nfet nch
propMatch := subType NM
termMap := D D G G S S B B
propMap := m simM
addProp := model nch

devMap := nfet nch_mac
propMatch := subType NV
termMap := D D G G S S B B
propMap := m simM
addProp := model nch_mac

devMap := nfet nch_25
propMatch := subType NH
termMap := D D G G S S B B
propMap := m simM
addProp := model nch_25

devMap := pfet pch
propMatch := subType PM
termMap := D D G G S S B B
propMap := m simM
addProp := model pch

devMap := pfet pch_mac
propMatch := subType PV
termMap := D D G G S S B B
propMap := m simM
addProp := model pch_mac

devMap := pfet pch_25
propMatch := subType PH
termMap := D D G G S S B B
propMap := m simM
addProp := model pch_25

devMap := capacitor nmoscap_25
termMap := PLUS PLUS MINUS MINUS
propMap := c c
addProp := model nmoscap_25

devMap := resistor rppolywo
termMap := PLUS PLUS MINUS MINUS
propMap := r res w w l l
addProp := model rppolywo

devMap := phyres rppolywo_m
termMap := PLUS PLUS MINUS MINUS SUB BULK
propMap := r res w w l l
addProp := model rppolywo_m
************************************************************

--
Thanks & Regards
---
Prabhakar. K
IC Layout Engineer
SoCtronics Tech. Pvt. Ltd.
Hyderabad - INDIA
e-mail: prabhu.usic@gmail.com
-
(-: 'GOAL' : Perhaps there's more than one way to reach it :-)
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Quek over 14 years ago

Hi Prabhakar

This is actually a common problem when importing resistors. If "r" is not available, we can also use the model name. Please make the following changes:

a. In the netlist, make the following modifications:

RR1 net9 net022 $SUB=gnd $[rppolywo_m] lr=20u wr=2u m=1 mf=1 mismatchflag=0

b. Use the following in the device map:

devMap := phyres rppolywo_m
propMatch := model=rppolywo_m
termMap := PLUS PLUS MINUS MINUS SUB BULK
propMap := w w l l
addProp := model rppolywo_m

Best regards
Quek
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Prabhu The ICL over 14 years ago

Hi! Quek,
I am very thankful to your kind & immediate response to
my questions ... Now the problem has resolved ... Once again Thank you
very much ...

--
Regards
---
Prabhakar. K
IC Layout Engineer
SoCtronics Tech. Pvt. Ltd.
Hyderabad - INDIA
e-mail: prabhu.usic@gmail.com

(-: 'GOAL' : Perhaps there's more than one way to reach it :-)
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Quek over 14 years ago

Hi Prabhakar

That's great. You are welcome. : )

Best regards
Quek
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