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Featured

What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?

Earlier this week I wrote about the electric vehicle (EV) transition, how it is happening…

Paul McLellan
• 7 min read
ota , Automotive , tier-1 , featured , zonal architecture

The Automotive Electric Vehicle Transition

The only really interesting part of the automotive industry is the electric vehicle…

Paul McLellan
• 8 min read
Automotive , Electrification , featured , ev , nev

Richard Goering, 1952-2023

I have some sad news to report. Richard Goering passed away last month at the age…

Paul McLellan
• 3 min read
featured , Richard Goering , EETimes
Breakfast Bytes

Latest blogs

The Most Important Operating System Ever

I wrote recently about Brian Kernighan's memoir and history in Brian Kernighan's…

• 7 min read
android , unix , iOS , MacOS , linux

Known Good Die

Do you know what known good die are? Do you know what wafer sort is? Final test?…

• 6 min read
system-in-package , kgd , 3DIC , known good die

Brian Kernighan's Memoirs

If you have ever worked on placement or floorplanning, and probably some other areas…

• 7 min read

System in Package, Why Now? Part 2

This post is a continuation of last week's post Multiple Die in Packages. Why Now…

• 6 min read
3DIC , more than Moore , moore's law

Cadence at CES 2020: Tensilica Everywhere

Once again, Cadence will be at CES in Las Vegas. It takes place January 7 to 10,…

• 4 min read
CES , Tensilica

Xcelium Is 50% Faster on AWS's New Arm Server Chip

At Re:invent, Amazon AWS announced Graviton 2, their second-generation Arm server…

• 3 min read
annapurna labs , nitro , cloud , aws , graviton 2 , cadence cloud , neoverse , ARM

Sunday Brunch Video for 8th December 2019

https://youtu.be/3gP0Z02MVps Made at Salinas River State Park (camera Carey Guo…

• less than a min read
sunday brunch

System in Package, Why Now?

At HOT CHIPS this summer, one of the things I noticed was just how many of the designs…

• 6 min read
chiplet , 3DIC , more than Moore , moore's law

Photonics Summit: Lumerical-Cadence Flow

James Pond, the CTO of Lumerical, wrapped up the Photonics Summit recently. He started…

• 3 min read
curvycore , Lumerical , silicon photonics , Virtuoso , photonics

"If You Can Get Your Ship into Orbit, You're Halfway to Anywhere"

I planned on using the 50th anniversary of Apollo 12 as a hook for this blog, but…

• 7 min read
rocket equation , space travel

Cadence to Acquire AWR

Yesterday Cadence announced that it has signed an agreement to acquire AWR from National…

• 3 min read
RF , awr , Virtuoso

The Photonics Summit 2019: Hybrid Lasers

Recently, Cadence held the fourth Photonics Summit and Workshop over two days. I…

• 5 min read
Lumerical , silicon photonics , photonics

Implementing Arm Hercules with Digital Full Flow

At Arm TechCon, there was a joint presentation by Arm, Cadence, and Samsung Foundry…

• 3 min read
Genus , hercules , Samsung , Innovus , ARM , full flow

2nd WOSET Workshop on Open-Source EDA

During ICCAD earlier in the month, there was the 2nd WOSET, which stands for Workshop…

• 4 min read
open source eda , openroad , woset

Verifying Processor Security, Part 2

This is the second post about Eli Singerman's keynote at the recent Jasper User Group…

• 5 min read
Jasper User Group , formal , Jasper , JasperGold , Formal verification

Formally Verifying Processor Security

Intel has had a couple of major events that totally changed their attitude to verification…

• 4 min read
Intel , Jasper User Group , formal , Jasper , JasperGold

OpenROAD: Open-Source EDA from RTL to GDSII

OpenROAD is a DARPA program to attempt to build a no-human-in-the-loop EDA flow,…

• 6 min read
ucsd , dod , openroad , andrew kahng , darpa

What Does P≠NP Mean?

Recently I wrote about computational software and said that EDA algorithms are all…

• 6 min read
NP-complete , computational software , np-hard

Die-to-Die Interconnect: The UltraLink D2D PHY IP

One of the big trends that has been happening somewhat below the radar is the growth…

• 5 min read
system in package , SiP , chiplet , more than Moore , 3D packaging

The 2019 Jasper User Group

Last week was the Jasper User Group meeting, the biggest annual gathering of formal…

• 4 min read
Jasper User Group , formal , Jasper , JasperGold , Formal verification

OpenTitan: Secure Boot with a Silicon Root of Trust

At HOTCHIPS last year, Google presented its security processor Titan. You can read…

• 3 min read
opentitan , open source hardware , google , open source

Computational Software

This is the third post in a series on computation in EDA and adjacent markets. The…

• 4 min read
computational software

Tempus Power Integrity Solution

One of the challenges in leading-edge nodes today is the resistivity of the interconnect…

• 3 min read
Tempus , Voltus , signoff

Dead Ends

Sometimes something comes along that looks like it is a portent of things to come…

• 7 min read
Automotive , Breakfast Bytes

IEDM 2019 Preview

Coming up in the beginning of December is the 65th International Electron Devices…

• 6 min read
IEDM

Computational Hardware

This is the second part of a three-part series of posts on computation. The first…

• 4 min read
computational software , computation

Computation and the Data Explosion

Everywhere you look these days, you get told that there is a data explosion going…

• 6 min read
computational software , computation

Implementing Automotive Radar on Tensilica Processors

The big controversy about sensors in autonomous driving is whether lidar is essential…

• 4 min read
Automotive , radar , fmcw , ADAS
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