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Featured

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Spectre 25.1 Release Now Available

The SPECTRE 25.1 release is now available for download at Cadence Downloads. For…

SpectreReleaseTeam
• 1 min read
featured , Spectre FMC Analysis , Spectre RF , Spectre Photonics , Spectre AMS Designer
Analog/Custom Design
Latest blogs

Virtuosity: 20(!) Things I Learned in June by Browsing Cadence Online Support

Wow! There was an amazing amount of new content added last month. A lot of new videos…

• 2 min read
AMS , Low Power , Virtuoso Space-based Router , VSR , MMSIM , SKILL for the Skilled , Virtuoso , Schematic Editor , Virtuosity , mixed signal , SKILL++ , Virtuoso Layout Suite , SKILL , Schematic

OpenAccess (OA) Based Flow - Efficient Implementation of Mixed-Signal Design for…

I had the great opportunity to represent Cadence at the Design Automation Conference…

• 2 min read
Solutions , DAC , cadence , Analog-Centric , Austin , Open Access , analog , VDI , Digital-Centric , Virtuoso , digital , oa , Encounter Digital Implementation , mixed signal , Texas Instruments , Mixed-Signal Methodology Book

SKILL for the Skilled: The Partial Predicate Problem

The partial predicate problem describes the type of problem encountered when a function…

• 6 min read
Team SKILL , programming , Jim Newton , IC615 , SKILL for the Skilled , continuation passing , partial predicate , CPS , Lisp , SKILL++ , SKILL

Virtuosity: 10 Things I Learned in May by Browsing Cadence Online Support

May was a big month for new videos. It was also a month that saw the release of Virtuoso…

• 1 min read
VLS GXL , Virtuoso Layout Suite L , Virtuoso , VLS L , Virtuoso Layout Suite , Virtuoso Layout Suite GXL , VLS XL , Virtuoso Layout Suite XL

Mixed-Signal -- Successful Tech-on-Tours, Huge Focus at DAC 2013

We just completed some hugely successful Mixed-Signal Tech-on-Tours in North America…

• 3 min read
real number modeling , clp , AMS Designer , CPF , Conformal Low Power , DAC 2013 , Mixed-Signal , Virtuoso , Internet of Things , amsDmvmv , mobile , PIEA , mixed signal , wreal , SMG , MDV , Schematic Model Generator , ARM Cortex-M , verification

SKILL for the Skilled: Part 9, Many Ways to Sum a List

In the previous postings of SKILL for the Skilled , we've looked at different ways…

• 9 min read
Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support

I'll confess: I didn't learn all of this strictly by browsing https://support.cadence…

• 2 min read
AMS , custom/analog , layout-dependent effects , Rapid Adoption Kit , 20nm , Virtuoso , Virtuosity , mixed signal , Custom IC Design

Things You Didn't Know About Virtuoso: Delta Markers in ViVA

This article is dedicated to the gentleman I sat next to at lunch at CDNLive a while…

• 3 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , IC615 , IC 6.1.5 , delta markers , Analog Design Environment , ViVA , Custom IC Design

SKILL for the Skilled: Part 8, Many Ways to Sum a List (Closures -- Functions with…

In the past several postings to this blog, we've looked at various ways to sum a…

• 8 min read
Team SKILL , lexical closures , programming , Jim Newton , closures , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support

Topics in March include advanced analysis in ADE GXL, taking advantage of lots of…

• 2 min read
Analog Design Environment , Virtuoso IC6.1.5 , Virtuoso Space-based Router , Rapid Adoption Kit , IC615 , IC 6.1.5 , ADE , VLS GXL , Virtuoso Analog Design Environment , Monte Carlo , Virtuoso Layout Suite L , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , VLS L , AMS simulation , Custom IC Design , modgens , RAKs , Virtuoso Layout Suite , Virtuoso Layout Suite GXL , VLS XL , SKILL , Virtuoso Layout Suite XL

Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two…

• 2 min read
AMS , EDI , CDNLive , CDNLive 2013 , MS ToT , cadence , tech on tour , mixed-signal IP , AMS Designer , analog , analog behavioral models , analog/mixed-signal , Virtuoso , mixed signal methodology guide , mixed signal , CDNLive SV 2013 , OpenAccess , SoCs , AMS Verification , mixed-signal verification

SKILL for the Skilled: Part 7, Many Ways to Sum a List

In this episode of SKILL for the Skilled I'll introduce a feature of the let primitive…

• 4 min read
Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support

February was a big month for RAKs (Rapid Adoption Kits)! If you haven't checked out…

• 3 min read
AMS , APS , Virtuoso Advanced Node , Virtuoso IC6.1.5 , IC 6.1 , Rapid Adoption Kit , Analog Simulation , Advanced Node , IC615 , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , variability , Spectre , Analog Design Environment , ADE-XL , Virtuosity , Custom IC Design , RAKs , Virtuoso Layout Suite GXL

"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

We are seeing a huge trend -- the mobile revolution is changing the way we go about…

• 4 min read
AMS , DVCon 2013 , CDNLive 2013 , SV-DC , Verilog-AMS , analog , Incisive , Mixed-Signal , smart devices , analog behavioral models , analog/mixed-signal , Virtuoso , Internet of Things , RNM , Verilog AMS , mixed signal , SenseAware , wreal , Virtuoso environment , Schematic Model Generator , mixed-signal verification

Virtuosity: 10 Things I Learned In January By Browsing Cadence Online Support

This month's highlighted content includes helpful information on wreal modeling,…

• 2 min read
Virtuoso Space-based Router , Rapid Adoption Kit , encounter , calibration , Virtuoso , Analog Design Environment , ADE-XL , AMS simulation , mixed signal , interoperability , wreal , Custom IC Design

Things You Didn't Know About Virtuoso: Drag and Drop

I love it when I'm sitting in a meeting with my colleagues or with a group of customers…

• 2 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , IC 6.1 , VIrtuoso drag and drop , IC 6.1.5 , ADE , Virtuoso , ViVA , ADE-XL , drag and drop , Custom IC Design

Introduction to Cadence Virtuoso Advanced Node Design Environment

What can designers do about advanced node technology? This is an introduction to…

• 6 min read
STI , Virtuoso Advanced Node , length of diffusion , custom/analog , Routing , analog prototyping , Double Patterning , layout-dependent effects , Ishikawa , custom , odd-loop marker , 20nm , Advanced Node , module generation , analog , WPE , design flow , LDE , dynamic coloring , LOD , well proximity , Placement , stress , interconnect layers , Custom IC Design , local interconnect

Virtuosity: 10 Things I Learned in December By Browsing Cadence Online Support

In addition to the R&D engineers who actually develop our software, the folks in…

• 4 min read
Variability Aware Design , AMS , Analog Design Environment , Virtuoso IC6.1.5 , Virtuoso Space-based Router , VSR , Analog Simulation , Cadence Space-based Router , workshop , IC615 , IC 6.1.5 , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , Schematic Editor , ViVA , ADE-XL , mixed signal , Custom IC Design , Virtuoso Layout Suite

Library "Safe Margins" -- Are They Really Saving Your Design?

Designers need to radically re-think their strategies for timing closure to get the…

• 4 min read
Standard Cell , memory characterization , Process Variation , Elzeftaki , library characterization , Timing Closure , Complex IO , PVT corners , safe margins , Complex Cell

SKILL for the Skilled: Part 6, Many Ways to Sum a List

In a previous post I presented sumlist_2b as a function that would sum lists of length…

• 5 min read
Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitmen…

Cadence holds a leading position in the EDA industry due to its broad product portfolio…

• 1 min read
CDNLive , cadence , AMS Designer , custom , Design Challenges , analog , web page , Mixed-Signal Methodology Guide , Mixed-Signal , Mixed-signal solutions web page , Virtuoso , mixed-signal book , digital , implementation , mixed signal , Encounter Digital Platform , web site , verification

Mixed Signal Technology Summit Proceedings Now Available

In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California…

• 5 min read
Static timing analysis , mixed-signal seminars , AMS , static analysis , EDI , microcontrollers , ARM Cortex M0 , mixed signal design , cadence , Functional Verification , mixed signal methodology , mixed signal solution , Open Access , STA , Verilog-AMS , timing model , FTM , Mixed-Signal , MCUs , encounter , Mixed-Signal Technology Summit , analog behavoral , analog behavioral models , analog/mixed-signal , mixed signal physical implementation open access , model validation , Signal Integrity , Virtuoso , Spectre , Cortex-M0 , oa , RNM , mixed signal methodology guide , real number types , Mixed signal physical implementation , behavioral models , mixed signal , OA: OpenAccess , cortex M , mixed-signal design , wreal , real number models , ARM , ARM-Cortex-M , OpenAccess , SPICE , mixed signal implementation , liberty model , simulation , AMS Verification

Mixed-Signal Technology Summit in Japan Provides Technology Updates

Japan’s semiconductor industry is undergoing a significant change in recent years…

• 3 min read
AMS , uvm , Virtuoso-AMS , microcontrollers , ARM Cortex M0 , mixed signal design , Mixed-Signal On Top , AMS-Designer , MS ToT , IC 6.1 , A/MS , mixed signal methodology , tech on tour , AMS Designer , analog on top , Open Access , Cortex-M , Verilog-AMS , analog , Mixed-Signal , encounter , Mixed-Signal Technology Summit , LDE , analog behavioral models , analog/mixed-signal , Virtuoso , mixed-signal book , Cortex-M0 , oa , ClioSoft , metric-driven verification , mixed signal , wreal , micro-controllers , ARM , ARM-Cortex-M , OpenAccess , Common Power Format , AMS Verification , TowerJazz , Matlab , real number

SKILL for the Skilled: Part 5, Many Ways to Sum a List

In the most recent posts of SKILL for the Skilled (see previous post here ) we looked…

• 5 min read
Team SKILL , Jim Newton , summing , Virtuoso , Lisp , SKILL++ , sumlist , SKILL

Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes

Are you working in the area of mixed signal? Then you may want to exchange information…

• 1 min read
ITDB , mixed-signal training , Andreas Lenz , analog on top , CPF , Mixed-Signal , encounter , Virtuoso , mixed signal , mixed-signal forum , OpenAccess , forum , Cadence Community

Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical…

The recently concluded ARM TechCon 2012 , the annual event for ARM users (including…

• 2 min read
ARM Techcon , EDI , chipestimate , ARM Cortex M0 , AMS Designer , ARM Technology Symposium , 20nm , 14nm , Mixed-Signal , Virtuoso , mixed-signal book , Cortex-M0 , mixed signal , mixed-signal design , ARM , ARM-Cortex-M

Recent Events Show That Customer Interest in Mixed-Signal Remains High

The well attended Mixed-Signal Technology Summit last month really demonstrated the…

• 2 min read
ARM Techcon , ARM Cortex M0 , mixed signal design , Technology on tour , MS ToT , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , Open Access , Cortex-M , Mixed-Signal , Mixed-Signal Technology Summit , analog/mixed-signal , mixed-signal book , Cortex-M0 , Mixed-Signal Tech Summit , mixed signal methodology guide , mixed signal , OA: OpenAccess , cortex M , mixed-signal design , ARM , Mixed-Signal Methodology Book , tech-on-tour , OpenAccess , AMS Verification

Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and…

A press release and a blog post caught my attention this week (October 15, 2012)…

• 2 min read
AMS , EDI , ets , uvm , microcontrollers , ARM Cortex M0 , Mixed-Signal On Top , MS ToT , cadence , AMS Designer , TSMC , EPS , Mixed-Signal , Virtuoso , mixed signal methodology guide , mixed signal , PVS , ARM , encounter power system , Encounter Timing System , IUS
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