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Featured

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Spectre 25.1 Release Now Available

The SPECTRE 25.1 release is now available for download at Cadence Downloads. For…

SpectreReleaseTeam
• 1 min read
featured , Spectre FMC Analysis , Spectre RF , Spectre Photonics , Spectre AMS Designer
Analog/Custom Design
Latest blogs

How Fred Discovered Mixed-Signal Behavioral Modeling

Introduction This is the first of a series of blogs where we will add pieces to the…

• 3 min read
AMS , mixed signal design , AMS-Designer , Verilog-AMS , analog , Mixed-Signal , Virtuoso , Fred , assertions , mixed signal , wreal

A Moment to Mourn -- John McCarthy, Father of Lisp

Here lies a Lisper Uninterned from this mortal package Yet not gc'd While we…

• 1 min read
John McCarthy , McCarthy , software development , Lisp , Custom IC Design , SKILL

SKILL for the Skilled: Introduction to Classes -- Part 3

In the previous posting Introduction to Classes -- Part 2 we saw the high level…

• 8 min read
Team SKILL , programming , Sudoku , classes , IC 6.1.5 , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Managing ECOs in Mixed Signal Designs

Imagine you are days away from completing the implementation of a fairly complex…

• 3 min read
ECO , Farhat , mixed signal design , CPF , Open Access , Floorplanning , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , Mixed signal physical implementation

SKILL for the Skilled: Introduction to Classes -- Part 2

In the previous posting Introduction to Classes -- Part 1 we introduced the problem…

• 3 min read
Team SKILL , programming , object orientation , Virtuoso , Lisp , SKILL++ , SKILL

Bringing Static Analysis Methods to Mixed Signal Designs

Accurate static analysis and complete coverage of the functional space remain very…

• 2 min read
Static timing analysis , static analysis , mixed signal design , full timing model , STA , timing model , analog , FTM , Mixed-Signal , Signal Integrity , OpenAccess , SPICE , liberty model , .lib

SKILL for the Skilled: Introduction to Classes -- Part 1

In the previous couple of SKILL for the Skilled postings, we looked at some of the…

• 3 min read
Sodoku , Team SKILL , programming , classes , object orientation , Virtuoso , object system , Lisp , Custom IC Design , SKILL++ , SKILL , Allegro

Virtuoso Analog Design Environment XL – Data Everywhere, But You Have a Review in…

In my previous blogs , I talked about productivity enhancing features of Virtuoso…

• 2 min read
analog , ADE , Virtuoso , Analog Design Environment , Virtuoso datasheets , Schematic Editor , Custom IC Design , datasheets

Things You Didn't Know About Virtuoso: Viva ViVA!

I realize that I have been quite remiss in that I have not yet blogged about the…

• 1 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , Analog Simulation , IC 6.1.5 , Virtuoso Analog Design Environment , Virtuoso , ViVA , ADE-XL , Custom IC Design

Synchronizing Designs and Behavioral Models in Mixed-Signal Flows

The creation of behavioral models is only one part of the process of using those…

• 3 min read
AMS , Virtuoso-AMS , mixed signal design , AMS-Designer , amsDMVAMS-Designer , Verilog-AMS , analog , Mixed-Signal , model validation , mixed signal , wreal

M/S Technology on Tour Blog – Model Validation and Assertion Based Verification

In February 2011, I had the opportunity to meet a group of analog and mixed-signal…

• 5 min read
Virtuoso-AMS , mixed-signal ToT , amsDMVAMS-Designer , Mixed-Signal , SVA , model validation , Virtuoso , PSL , assertions , mixed signal

How to Design Analog/Mixed Signal (AMS) at 28nm

Wireless, networking, storage, computing and FPGA applications have been moving…

• 3 min read
AMS , AMS v2.0 , APS , Virtuoso-AMS , IP , AMS-Designer , reference flow , 28nm , TSMC , analog , Mixed-Signal , LDE , Virtuoso , Spectre , mixed signal

Mixed-Signal Physical Design Implementation Made Easy

Getting a complex mixed-signal design assembled and completely analyzed for mask…

• 2 min read
Low Power , IC 6.1 , Floorplanning , Mixed-Signal , encounter , Virtuoso , mixed signal , OpenAccess , design implementation

Virtuoso Analog Design Environment XL – Make Friends with Variation

In my last blog, Virtuoso Analog Design Environment XL - Embrace the Productivity…

• 3 min read
PVT , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Analog Simulation , Corners analysis , analog , IC 6.1.5 , ADE , worst case corners , Virtuoso Analog Design Environment , Monte Carlo , Virtuoso , ADE-GXL , ADE-XL , Custom IC Design

SKILL for the Skilled: Virtuoso Applications of SKILL++

In this posting, I continue looking at applications of SKILL++. In particular, I…

• 4 min read
Team SKILL , Virtuoso IC6.1.5 , closures , IC 6.1.5 , sort , Virtuoso , Lisp , Custom IC Design , SKILL++ , sorting , SKILL

CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)

We have been talking about low power simulation and the Common Power Format (CPF…

• 2 min read
Low Power , CPF , Verilog-AMS , analog , Mixed-Signal , Spectre , Connect Module , mixed signal , wreal , SPICE

Virtuoso Analog Design Environment XL – Embrace the Productivity

In my last blog, Virtuoso IC 5.1.41 was Good but Virtuoso IC6.1 is Better , I wrote…

• 4 min read
parasitic-aware design , Analog Design Environment , PAD , Virtuoso IC6.1.5 , Analog Simulation , analog , IC 6.1.5 , ADE , ADEnalog , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Parasitic analysis , Custom IC Design

SKILL for the Skilled: Sorting With SKILL++

In the previous couple of SKILL for the Skilled postings we looked at some of the…

• 6 min read
Team SKILL , programming , functions , sort , Virtuoso , SKILL++ , sorting , SKILL

Thing You Didn't Know About Virtuoso: Redux

After a long break, I'm going to try to venture back into the blogosphere, starting…

• 1 min read
Virtuoso IC6.1.5 , Search Assistant , IC 6.1 , Navigator , IC 6.1.5 , Virtuoso , Property Editor , Custom IC Design , Schematic-driven Layout , Schematic

Analog IP Verification - A Reference Guide to Practices Used

I have had a lot of discussions recently around improving the final integration of…

• 1 min read
AMS , Analog Design Environment , mixed-signal simulators , Analog Simulation , analog , IC 6.1.5 , ADE , assertion , AMS simulation , assertions , mixed signal

Will Evolving Language Standards Address Mixed-Signal Verification Problems?

Mixed-signal verification has been one of the hottest topics in the past year, and…

• 6 min read
SystemVerilog , AMS , assertion-based , SV-DC , analog , ADE , Mixed-Signal , SVA , DMS , Accellera , mixed signal , A-SVA

Virtuoso IC 5.1.41 Was Good but Virtuoso IC 6.1 is Better

With the recent release of unified custom/analog flow that is based on the latest…

• 3 min read
Analog Design Environment , Virtuoso IC6.1.5 , IC 6.1 , analog , Constraint-driven , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Custom IC Design , SKILL++ , SKILL

Is China Ready for Next Generation Mixed-signal Design?

A Chinese design engineer told me that his manager once told him: "You do not have…

• 4 min read
China , mixed-signal ToT , tech on tour , abstraction , EDA360 , analog , Mixed-Signal , Convergence , intent , japan , Silicon Realization , mixed signal , SoCs

Rapid Analog Prototyping - Handcrafted Layout Gets a Needed Productivity Boost

As more and more custom/analog designs migrate to advanced process nodes (<65nm)…

• 4 min read
AMS , parasitic-aware design , PAD , RAP , Virtuoso IC6.1.5 , custom/analog , PCells , Advanced Node , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , rapid analog prototyping , Custom IC Design , modgens , Virtuoso Layout Suite , parasitics

Early Analysis is Key – Parasitic-Aware Design

Decreasing geometries and increasing design complexity are making the task of designing…

• 3 min read
parasitic-aware design , Analog Design Environment , PAD , Virtuoso IC6.1.5 , IC 6.1.5 , ADE , Virtuoso , ADE-GXL , ADE-XL , parasitics

Virtuoso IC6.1.5: Software and Fine Red Wine

Software, like fine red wine, can get better with age as well -- but it requires…

• 7 min read
AMS , parasitic-aware design , Low Power , Virtuoso IC6.1.5 , custom/analog , Analog Simulation , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , mixed signal , Custom IC Design , DFM , parasitics

Q&A: IBM Modeling Team Describes Advanced SOI Qualification Flow In Cadence MMSIM…

Circuits implemented using sub-micron technologies require designers to meet tighter…

• 9 min read
APS , characterization , Compact Modeling Council , model qualification , IBM , MMSIM , Monte Carlo , spectreMDL , Spectre , CMC , SOI , Custom IC Design , Spice model verification , BSIMSOI

Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 2)

The design and verification methodology for analog circuits has not changed much…

• 3 min read
ABV , assertion-based , Analog Simulation , analog , SoC , Mixed-Signal , SVA , PSL , AMS simulation , assertions , mixed signal , wreal , Custom IC Design , verification
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