Custom IC Design Blogs

A couple of years ago, we released the revamped and improved Virtuoso ADE Verifier. We are sure you must be familiar with its various benefits. Just to recap what we have already shared through various channels such as videos, documentation, and earlier blogs, Virtuoso ADE Verifier helps you manage your project flow at different verification stages by performing implementation and requirement-driven verification of analog and mixed-signal designs. Add to this the fact that this verification can be done in a top-down, bottom-up, or mixed mode in a verification project. Such a project can have multiple verification requirements owned by multiple teams across an organization group. The Virtuoso ADE Verifier cockpit helps you establish mappings between requirements and their corresponding simulation implementations for gathering accurate results. You can then review the overall verification status at the desired hierarchy level.

So, the next question that might come to your mind is, why do we need reliability in Virtuoso ADE Verifier, when it can do all this and more already?  

If you are a frequent user of the analog design environment products such as Virtuoso ADE Assembler or Virtuoso ADE Explorer, you may be familiar with reliability analysis and its use to analyze the effect of time on circuit performance drift. The need for performing reliability analysis has gained importance to predict the degradation of designs with the passage of time or due to self-heating effects. You might have run reliability analysis in Virtuoso ADE Assembler or Virtuoso ADE Explorer to generate fresh (at time zero), stress (involving degraded output), and aged (over a specified time interval in years) results.

You will be glad to know that since IC6.1.8 ISR12 and ICADVM18.1 ISR12, Virtuoso ADE Verifier also supports reliability outputs in an implementation hierarchy. Using these outputs you can verify the design degradation and performance over a time span in accordance with your verification plan.

But how are these outputs enabled or selected? The answer is right there in the Virtuoso ADE Verifier Preferences form. All you need to do is enable the reliability analysis in Virtuoso ADE Assembler or Virtuoso ADE Explorer, and at the same time, in Virtuoso ADE Verifier, select the preferences that correspond to the type of outputs for which you want to see results. These preferences are controllable using environment variables, making them all the more easy to use.  

It is important to emphasize that when adding reliability results to Virtuoso ADE Verifier, you take a call on what is really essential for your final verification results. Reliability simulations tend to create a large amount of data but when you use this information in Virtuoso ADE Verifier, it is important to focus only on the data that you need for your verification. Using the preferences related to reliability outputs, you can filter the Reliability results down to see only the required pieces. For example, you might not want to view the fresh or stress results, but you might want to focus only on the 10-year results from aged runs.

Assuming that you select the preferences that enable reliability outputs for all ‘fresh’, ‘stress’, and ‘aged’ tests for a Virtuoso ADE Verifier implementation, you see outputs that are similar as the image below:

Reliability in Virtuoso ADE Verifier supports both ‘Single Run, Sweeps and Corners’ as well as ‘Monte Carlo Sampling’ simulation methods specified in Virtuoso ADE Assembler. Simulations run using the Monte Carlo Sampling method involving ‘1+N’ and ‘N+N’ mapping flows show reliability outputs similar to the image below:

In ‘1+N’ mode, MC variation is applied for both ‘stress’ and ‘age’ simulation results. On the other hand, in ‘N+N’ mode, first a single stress simulation is run to calculate the aging degradation. This simulation is reused with process variation during MC analysis for aging.

Again, Reliability analysis within RunPlan run mode can also be used in Virtuoso ADE Verifier to define your implementations, where each Run Plan can have its own Reliability test defined with its corresponding Output and/or Statistical values such as in the image below:

Finally, when you run the reliability-enabled flow in Virtuoso ADE Verifier, you might see reliability implementation results similar to the image below: 

If you want to try out and understand the reliability analysis flow in Virtuoso ADE Verifier, check out the Reliability in Virtuoso ADE Verifier video on the Cadence Support portal.    

Related Resources

For more information on Cadence circuit design products and services, visit www.cadence.com.

Contact Us

For any questions, general feedback, or even if you want to suggest a future blog topic, write to custom_ic_blogs@cadence.com.

Happy reading, and stay safe!

Harsh Gupta

Rashmi Girdhar

About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso technology. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of the Virtuoso environment, and a lot more. To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.