The Voltus IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow.

The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high performance, accuracy, and capacity for next-gen chip designs.

In July 2019, when I became aware of the 17 Sustainable Development Goals (SDGs) adopted by all United Nations Member States, I knew that the IC design industry was going to play a major role in working towards achieving the 13th goal, Climate Action. The primary reason is that power management is the critical area in chip design that has a cascading effect on energy conservation across systems.

With all industry leaders, including Cadence adopting the target and actively working with the Science Based Targets initiative (SBTi), there is a clear path to success. The crucial question to be answered is: “How can a designer limit warming to 1.5°C ?”  The power consumed by the IC directly contributes to Scope 2 carbon footprint. The higher the power consumed, the higher will be the heat generated, which in turn needs more power for cooling.

This is where the importance of RTL power estimation and harnessing it for power and IR drop signoff comes into the picture. The RTL architecture team first optimizes the power consumption of the design and then hands it over to the implementation team to achieve the power, performance, and area (PPA) target. With the ever-increasing complexity of ICs, balancing the power and performance is not an easy task. One cannot compromise on the performance—even a microsecond delay in a collision sensor can cause havoc in the event of a car crash. So, let’s look at how power consumption can be reduced without impacting the performance of the chip.

Traditionally, the IR signoff team relied on the vectorless approach that assumes some activity factor for sequential elements, macro output, and inputs ports of a block. The activity is then applied based on the software algorithm and is propagated to the output logic cone, leading to higher power consumption and local IR hotspot for blocks. These results have a direct impact on the area as designers tend to add more decaps and power stripes to mitigate the IR drop or downsize cells to reduce the power. Utilizing vectors developed during RTL testing provides a middle path to balance power without compromising on performance. Since these vectors are developed along with RTL, they can be used from the clock tree synthesis (CTS) stage for keeping a check on the power consumption. With superior testing modes, we can now perform more accurate RTL power estimation of multi-billion gate SoC designs. It will be even better if one can emulate the entire functioning of the IC and provide those vectors that cover the chip behavior extensively.

Let us now see how all these processes work together. The emulator has a vector format that is different from any other functional simulator. The number of gates synthesized from RTL completely differs from what goes out on Silicon. This is where Cadence's Intelligent System Design strategy comes into play. It does not matter whether your vector is a zero delay or unit delay, Voltus IC Power Integrity Solution can read and apply the delay accordingly. Whether the vector format is FSDB, VCD, SHM, PHY, TCF, or SAIF, the Voltus solution can read them seamlessly and support a mix and match of these formats.

Voltus is capable of mapping the name of the RTL flop with the gate netlist, and its auto-mapping algorithm is able to match more than 95% of the modified flop names.

Once the flop and macro names are mapped correctly, its activity then gets propagated to the combinational logic cone, thereby giving a correct estimate of the power. In one of our customer blocks, I observed that the vectorless power analysis reported more than 1W of power. However, in the same design with 99% flop mapping and logic propagation, the power was around 900mW. Had the designer followed the vectorless path, they would have definitely over-designed the block to meet the expected performance.

We can clearly see that with the RTL-based power analysis, a designer can achieve better PPA, reduce power consumption, and enable sustainable innovation for our next-generation technologies.  

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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