Featured

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
Digital Design
Latest blogs

ECO with Stratus HLS and the Digital Implementation Flow

For years chip designers have dealt with ECO’s when their source code was written…

• 4 min read
High-Level Synthesis , ECO , Conformal ECO Designer , Stratus , HLS

What's in it for Me in Innovus 18.10 Release?

At advanced nodes, there’s always a deep conflict between power, performance, and…

• 1 min read
Digital Implementation forums , Tempus , Release Page , Cadence Online Support , Digital Implementation , Innovus , full flow , blog

QoR with High-Level Synthesis. Can it really be better than hand-coded RTL?

Whenever we talk to potential customers about Stratus HLS , we usually mention that…

• 4 min read
High-Level Synthesis , Stratus , SystemC , HLS

A Decade of Building CODECs with High-Level Synthesis

Over the past decade, we have seen a dramatic increase in the size of common video…

• 6 min read
High-Level Synthesis , Stratus , SystemC , HLS

High-Level Synthesis: The Secret Is Out

Gone is the day when companies (our customers) kept their use of high-level synthesis…

• 2 min read
High-Level Synthesis , CDNLive , Stratus , HLS

Wind of Change in Hardware Design

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I…

• 2 min read
High-Level Synthesis , deep learning , machine learning , Stratus , HLS

Wondering How Moving To Advanced Nodes Might Affect Manufacturability And Yield?

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose…

• 1 min read

Get Early Silicon Learning to Accelerate Yield Ramp-up

How important is it for your advanced node products to get early silicon learning…

• 2 min read
DNA , pattern analysis , machine learning , silicon learning , yield , test chip , design for manufacturing , DFM

Cadence Modus DFT at International Test Conference 2017

While DAC is the focal point for the EDA industry, the test community travels in…

• 1 min read
Automotive , DFT , modus , ATPG , diagnostics , ITC

How to Measure and Improve Design Regularity for Better Yield

The following post is an excerpt of “Methodology for Analyzing and Quantifying Design…

• 1 min read
pattern analysis , machine learning , analytics , yield , silicon signoff , design for manufacturing , DFM

Functional Correctness—The Forgotten Benefit of HLS

I like to ask questions, because you learn a lot that way. In fact, I did a survey…

• 2 min read
High-Level Synthesis , Digital Implementation , HLS , verification

Faster and Smarter

At the Cadence VIP dinner at Korea CDNLive last month, Paul Cunningham spoke about…

FormerMember • 1 min read
cdnlive korea , deep learning , CDNLive , machine learning , digital , signoff

Why Pegasus Is the Biggest Breakthrough in SoC Physical Verification in 20 Years…

These days, DRC rule deck availability for the market tools is not a major issue…

• 3 min read
Physical verification , massively scalable , pegasus , DRC , Cloud ready

2017 Annual HLS Survey Results

As many of you know, Cadence (more correctly, “I”) recently performed an industry…

• 4 min read
High-Level Synthesis , survey , Stratus , HLS

Designing for Low Power… Begin at the Beginning

So you have your RTL written, and it’s time to optimize to reduce power. If that…

• 3 min read
Low Power , high level synthesis , power , HLS

Let Your DRC Fly! Cadence Announces Breakthrough in SoC Physical Verification

This morning we announced our next-generation Pegasus Verification System, the biggest…

• 2 min read
Physical verification , CDNLive , pegasus , DRC , design rule check , silicon signoff

“Great” Hardware Design in a Wireless World

As part three of the “ Making Hardware Design Great Again” series , let’s see how…

• 4 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Have DRC Tools Run Out of Steam? – Part 2

We are continuing the physical verification blog posts with more questions we hear…

• 3 min read
massively scalable , DRC , multithread , distributed processing

Have DRC Tools Run Out of Steam? – Part 1

In the EDA history of design rule check (DRC), there have been two distinct eras…

• 3 min read
Physical verification , DRC , design rule check

Making Hardware Design Great Again in 2017 - Part Deux

In part one of this series, we talked about the role of the hardware designer , specifically…

• 5 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Making Hardware Design Great Again in 2017

Ok, I admit it… that title is a blatant attempt to grab your attention. But it should…

• 4 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Performance, Power, Area. It's All You Need to Know—or Is It?

Whether it's in a technical paper, a pundit's article, or a live discussion with…

• 2 min read
High-Level Synthesis , PPA , Stratus , SystemC , HLS

Five-Minute Tutorial: Innovus Clock Tree Synthesis and Debugger

Hi Everyone, Last time, our Five-Minute Tutorial focused on the new Innovus Placement…

• less than a min read
training , ccopt , clock tree synthesis , debugger , Digital Implementation , Innovus

Hot Summer for the High-Level Synthesis Community

Summer is usually a slow time of the year due to vacations, beautiful weather, and…

• 4 min read
High-Level Synthesis , DAC 2015 , SystemC , Brian Bailey , HLS , SystemC Japan 2015

Five-Minute Tutorial: Innovus Placement Optimization

Hi Everyone, Last time we got a quick look at The Innovus Standard Flow . Now…

• less than a min read
GigaPlace , Timing Optimization , Innovus , Placement

Five-Minute Tutorial: The Innovus Standard Flow

Hi Everyone, Last week I highlighted a video featuring Innovus User Interface…

• less than a min read
design flow , Digital Implementation , Innovus , five minute tutorial

Five-Minute Tutorial: Innovus User Interface Tips

Hi Everyone, No doubt by now you have heard about the Innovus Implementation System…

• less than a min read
UI , Digital Implementation , Innovus , five minute tutorial

Five Things You Didn’t Know About High-level Synthesis

Most of you have heard about the promises of high-level synthesis (HLS). Things like…

• 4 min read
High-Level Synthesis , ECO , Conformal ECO Designer , cadence , Blu Wireless , Forte , Stratus , HLS
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