Featured

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design
Latest blogs

Demo: Partitioning a Design in SoC-Encounter

One of the longest standing capabilities in SoC-Encounter is its ability to partition…

• less than a min read
SoC-Encounter , partitioning , hierarchical design , screencast , Digital Implementation

Getting Started with dbGet

If you've been checking out the other blogs here in the Digital Implementation community…

• 2 min read
database access , SoC-Encounter , dbGet , dbSet

An Interview with Global Timing Debug Architect Thad McCracken

So who is Thad McCracken and why should you be interesting in reading this blog entry…

• 8 min read
SoC-Encounter , Ostrich , Global Timing Debug

createPGPin to the rescue: getting the power pins you want in your block LEF

Hi Everyone! Welcome to my first blog post! My plan for this space is to share with…

• 2 min read
SoC-Encounter , lefOut followpins , LEF , createPGPin

Demo: Calling Global Timing Debug for a Single Path

Global Timing Debug has been a very popular capability within SoC-Encounter. Once…

• 1 min read
SoC-Encounter , STA , screencast , Digital Implementation , Global Timing Debug

Interview: CDNLive! People’s Choice Winner Jason Gentry

At the recently completed CDN Live! Silicon Valley 2008 user conference, I had a…

• less than a min read
dbGet , robust data access , CDNLive! , "SoC-Encounter"

Running SoC-Encounter...from an iPhone

Hello from CDNLive Silicon Valley 2008! I've had a great few days out here interacting…

• less than a min read
SoC-Encounter , iPhone Cisco VPN Client , Mocha VNC Lite , iPhone

Need for dynamic IR drop analysis at floor and power planning stages?

Here is a question for all the power grid designers out there: Do you see the need…

• 1 min read
dynamic rail analysis , Early Rail Analysis , Cadence Encounter Power System , Digital Implementation

Effectively communicating Low-Power and Power-Efficient Design knowledge

For those of you interested in the Power space I recently had an article published…

• less than a min read
Low-Power , Power-Efficient Design , Logic Design , Digital Implementation

Demo: Interactive Floorplanning in SoC-Encounter

In this demonstration, we'll show how to perform the following actions: Resize a…

• less than a min read
SoC-Encounter , screencast , Rectilinear Cut , Floorplanning and Prototyping

Demo: How To Make Multiple Edits with "Apply All" in SoC-Encounter

Today, I'm starting what I hope will be a series of screencasts where I demonstrate…

• less than a min read
SoC-Encounter , screencast , Digital Implementation , Apply All , Attribute Editor

Understanding Clock Net Markings in SoC-Encounter

I'm happy to report that the Digital Implementation Forums are picking up momentum…

• 3 min read
dbGet , Digital Implementation forums , CTE-TCL , encounter , clocks , saveClockNets

See you at CDNLive! Silicon Valley

Are you planning to attend this year's CDNLive! Silicon Valley 2008? Please leave…

• less than a min read
cadence.com community , First Encounter , CDNLive!

Who Designed the iPhone?

When people ask you what you do for a living, is your response as clumsy as mine…

• 1 min read
Digital Implementation , iPhone

Statistical Timing Analysis - Has its time arrived?

At 45nm chip designs, manufacturing and process control becomes increasingly difficult…

• 2 min read
Static timing analysis , STA , Digital Implementation , SSTA , corner analysis

Customer Experiences With Low-Power Design

Hello and welcome to the new Cadence community site, and my first blog post. You…

• 4 min read
Low-Power , Logic Design , Digital Implementation , The Power Forward Initiative

The Case for Robust Database Access

The most frequently viewed forum post in the old cdnusers.org "Digital IC->Floorplanning…

• 3 min read
First Encounter , Hierarchical Module Ports , robust data access , Digital Implementation , CTS
Blog - Title