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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Struggling with Coverage Convergence – Give your Verification Wings with Xcelium…

Functional verification consumes more than 70% of the labor invested in today’s SoC…

• 1 min read
coverage , machine learning , xcelium , simulation

USB4 Interoperability with Thunderbolt™︎ 3 (TBT3) Systems

One of the key goals for USB4 is to retain compatibility with the existing ecosystem…

• 2 min read
Verification IP , USB4 VIP , usb4 , usb4 router

Moving Beyond EDA: The Intelligent System Design Strategy

The rising customer expectations, intermingling fields and high performance needs…

• 5 min read
optimality , artificial intelligence , featured , intelligent system design

TSN-PTP: A Real-Time Network Clock Synchronizing Protocol

In a network containing multiple nodes, the need for synchronization between the…

• 2 min read
Verification IP , uvm , 5G Network , Ethernet VIP , Functional Verification , Cadence VIP portfolio , VIP , Automotive Ethernet , Ethernet , TSN , PTP , precision timing protocol , verification

Flash Toggle NAND 4.0 in a Nutshell

NAND Flash memory is now a widely accepted non-volatile memory in many application…

• 2 min read
Verification IP , Memory , flash , VIP , verification

Achieve 80% Less Late-Stage RTL Changes and Early RTL Bug Detection

It has become challenging to ensure that the designs are complete, correct, and adhere…

• 5 min read
featured , Jasper RTL Designer Signoff App , Jasper , Early Bug Detection

JEDEC UFS 4.0 for Highest Flash Performance

Speed increase requirements keep on flowing by in all the domains surrounding us…

• 2 min read
Verification IP , Memory , UniPro , MIPI Alliance , IoT , VIP , JEDEC , UFS , storage , MPHY

Coalesce Xcelium Apps to Maximize Performance by 10X and Catch More Bugs

Xcelium Simulator has been in the industry for years and is the leading high-performance…

• 1 min read
performance , featured , SoC , apps , xcelium , simulation , verification

Stay Ahead of Competition with Real-Time Cross-Team Collaborations

To stay ahead in competition in chip design real-time collaborations ensure traceability…

• 4 min read
collaboration , Palladium , verification management , Traceability , vManager

Xcelium PowerPlayBack App and Dynamic Power Analysis

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay…

• 5 min read
Dynamic Power Analysis , xcelium , power

Jasper C2RTL App for Datapath Verification

Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every…

• 5 min read
Datapath Verification , c2rtl , Jasper C2RTL , Equivalence Checking

Cadence in Collaboration with Arm Ensures the Software Just Works

The increase in compute and data-intensive applications and the need for lower power…

• 6 min read
SBSA , Emulation , Pre Silicon compliance Testing , Arm SystemReady

Automotive Revolution with Ethernet Base-T1

The automotive industry revolutionized the definition of a vehicle in terms of safety…

• 2 min read
Automotive , Verification IP , PTPOverMacSec , 100BaseT1 , uvm , Ethernet VIP , Functional Verification , Cadence VIP portfolio , VIP , Automotive Ethernet , 10BaseT1 , e , Ethernet , TSN , PTP , BaseT1 , 1000BaseT1 , Ethernet PHYs , MacSec , verification

Data Integrity for JEDEC DRAM Memories

With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b and…

• 3 min read
Verification IP , ddr5 , Memory , DDR5 DIMM , VIP , JEDEC , DRAM , lpddr5 , data integrity , NVDIMM , verification

5X “Time Warp” in Your Next Verification Cycle Using Xcelium Machine Learning

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated…

• 1 min read
xcelium ml , machine learning , xcelium , simulation

Quest for Bugs – The Constrained-Random Predicament

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of…

• 2 min read
compression , throughput , machine learning , Hard to Hit Bin , Coverage Closure , Regression , simulation

Modeling Configuration in PSS (Portable Stimulus)

Design patterns for modeling configuration and reconfiguration in PSS (Portable Stimulus…

• 4 min read
configuration , Perspec , portable stimulus , verification

Virtual Platforms to Shift-Left Software Development and System Verification

It is always beneficial to detect the defects early in the development phase prior…

• 5 min read
Virtual System Platform , virtual prototypes , helium

Leveraging Jasper UNR App for Code Coverage Signoff

Broadcom developed a code coverage signoff flow using Xcelium simulator’s constant…

• 5 min read
Jasper UNR app , System Design and Verification

Demystifying CXL.cache

If you have worked with Peripheral Component Interconnect Express (PCIe) in the past…

• 3 min read
CXL , Functional Verification , pcie 5 , VIP , PCIExpress , coherency , verification

Renesas Leverages Palladium + System VIP Solution for System Verification and Performance…

Verifying bus performance by analyzing bandwidth and latency over time in chips is…

• 5 min read

Enflame Accelerates the DFT and DFD Verification using Palladium

DFT (Design for Testability) provides the much-needed support to the manufacturers…

• 5 min read

How AMBA CHI Specification Has Evolved - CHI-E (r)evolutionary?

We covered CHI specification revisions A to D in my previous article , what about…

• 2 min read
Verification IP , Functional Verification , VIP , AMBA , CHI VIP

System Verification Scoreboard: Its Role and Partnership with Verification IPs

As discussed in the last installment of the blog, a robust system level scoreboard…

• 1 min read
Verification IP , scoreboard , SoC verification , Hardware Coherency

AMBA Distributed Translation Interface (DTI) for Arm System MMU

In ARM MMU-based systems, DTI protocol defines a standard way to communicate with…

• 1 min read
AMBA-DTI , AMBA VIP , AMBA Verification IP

Device Training for High Speed DRAMs

As the device frequencies and the data rates go up with every new generation of Interface…

• 3 min read
Verification IP , ddr5 , VIP , JEDEC , Training Modes , lpddr5 , lpddr5x , memory models , DDR5DIMM

LPDDR5 Verification from PHY to System Level

LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system…

• 6 min read

How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device?

DDR Memory is an important part of a wide array of electronic system designs in various…

• 2 min read
Verification IP , Industry Insights , Functional Verification , DFI 5.1 , VIP , SoC , DFI , storage , DFI Technical Group , memory models , DDR-PHY , DDR-PHY Interface
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