Functional Verification Blogs

USB is one of the most widely used interfaces in the PC market for more than 20 years. Though it remains the same form in laptops and servers, it never stops its evolution in terms of capacity and speed. Embedded USB2.0, known as eUSB2, was created to address the concerns of power efficiency and portability. Although eUSB2 largely reuses USB2.0 protocol layer, the verification of eUSB2 can be never thought of as a miniature...

Since 2013, we have seen the HBM specifications being released by JEDEC and companies announcing in the same month HBM products just like magic. How can these companies have a silicon-proven product altogether with newly announced official specifications? What is the secret process they use in order to be constantly first-in-market with these new technologies? And more important, what can YOU do in order to also be such...

Our customers’ tests have become more complex, longer, and consume more resources than before. This increases the need to optimize the regression while not compromising on coverage. Some advanced customers of Specman use Machine Learning based solutions to optimize the regressions while some use simpler solutions. Based on a request of an advanced customer, we added a new Coverage API in Specman 19.09 called Coverage...

Curious about what’s going on behind the scenes with verification? Bernard Murphy, Jim Hogan, and our own Paul Cunningham are on the case with the “Innovation in Verification” blog stream over at semiwiki.com . Every month, this trio reviews a newly-published paper in academia that pertains to verification and discusses its implications. Be sure to stop by—it’s a great place to see what might be coming down the pipeline...

Looking to learn? There's a bunch of new RAKs (Rapid Adoption Kits) available online now! 1) Indago 19.09 Better Driver Tracing and More Are you new to Indago and not sure where to start? Luckily, there’s a new Rapid Adoption Kit for you: the Indago 19.09 Overview RAK! This neat package contains everything you need to get your debugging started through Indago. In four short labs, plus a brief introductory lab, you...

Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality. The diagram below shows two lane adapters connected to each other and each going through the link training process. Each training sub-state transition is contingent on conditions for both transmission and reception of relevant ordered sets...

We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab GmbH, describe how he added Specman/e syntax to Sublime Text 3: According to the 2018 StackOverflow Developer Survey , the popularity of development environments (IDEs, Text Editors) among software developers shows the following ranking: Visual Studio Code 34.9% Visual Studio 34.3% Notepad++ 34.2% Sublime Text 28.9% Vim...

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each ingress adapter. An entry of a routing table maps an incoming HopID, called Input/Ingress HopID to a corresponding pair of Output/Egress Adapter and Egress/Output HopID. The responsibility of programming routing tables lies...

In the former blog about Python and Specman: Specman: Python Is here! , we described the technical information around Specman-Python integration. Since Python provides so many easy to use existing libraries in various fields, it is very tempting to leverage these cool Python apps. Coverage has always been the center of the verification methodology, however in the last few years it gets even more focus as people develop...

Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP, or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled...

If you missed the first part of this series, you can find it here . So: what does Green Hills Software propose we do? The issue of “solving security” is, at its core, impossible—security can never be 100% assured. What we can do is make it as difficult as possible for security holes to develop. This can be done in a couple ways; one is to make small code in small packs executed by a “safing plan”—having each individual...

Autonomous vehicles are coming. In a statistic from the U.S. Department of Transportation , about 37,000 people died in car accidents in the United States in 2018. Having safe, fully automatic vehicles could drastically reduce that number—but the trick is figuring out how to make an autonomous vehicle safe. Internet-enabled systems in cars are more common than ever, and it’s unlikely that the use of them will slow or...

Emulators are great. They vastly speed up verification to the point where it’s hard to imagine life without them; as designs grow in complexity, simple simulation can’t keep up for the biggest designs. The extra oomph from emulation is almost a necessity for the top percentages of design sizes. However, many users of Palladium aren’t efficiently using their unit’s processing power, and as a result they’re missing out...

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019. What people refer to as “the cloud” is commonly divided into three categories: Infrastructure...

Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore at the Cadence Theater...

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions...

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving. With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex...

Welcome back to this account of the IP Security Panel at the Accellera Luncheon at DAC 2019. We’ve covered who’s seated on the panel and the moderator’s questions in the last installment (link to first blog)—now it’s time to talk about what the audience had to ask. The first question asked was related to that morning’s keynote speaker, and that speaker’s one criteria for IP developers with regards to security: do they...

Figure 1: The panel and crowd Citizens—the tech world is in trouble. With the ever-expanding size and complexity of chip designs, security hasn’t kept up. Old techniques for securing a design are no longer sufficient—and with IoT devices expanding into every facet of a person’s life, security is more important than ever. The often-joked-about case of someone hacking your refrigerator isn’t strictly a joke—without...

The knowledge and experience of using Specman/ e tells everyone that you have acquired profound verification methodology. But how do you showcase this knowledge to your company, colleagues, and perspective employers? To help you showcase your expertise, Cadence Training Services now offers Cadence Digital Badging . A certification test was created for some technologies (including Specman). When you pass the certification...

Do you know from where Python technology gets its name? It is not from the snake, it is named after the Monty Python comedy group. And indeed, one of the main guidelines behind it is to be fun to use (check out the Zen of Python ). Therefore, Python is intuitive, readable, and easy to learn - all of these make it not only fun to use but also highly productive. Does this sound familiar? If you are an e user, it should...

If you’ve got security on the mind—and in this day and age, who doesn’t?—and you’re planning to attend DAC, be sure to stop by the Accellera-sponsored Luncheon Focusing on IP Security Assurance Issues Led by Panel of Industry Experts. There, you’ll hear a short update on what Accellera’s been up to by Accellera Chair Lu Dai, and then the experts will jump right into a panel discussion covering all sorts of IP security...

On May 23rd, 2019, Cadence announced that Thinci has elected to use the complete Cadence Verification Suite to speed up the verification of their machine-learning and AI designs. Now, Thinci can access the new technologies available through the Cadence Verification Suite to shorten their product development time by months while improving verification coverage. “We selected the Cadence Verification Suite because it...

In the previous blog: Concurrent Actions in Specman , we discussed the existing options: all of ( which awaits completion of all branches) and first of (which terminates at the first completion of any branch). In 19.03 we added enhancement on top of these existing options, we made them more dynamic. In all the examples in the previous blog, the number of branches was constant (all the examples used 2 branches). What...

The Red Hat Summit is coming around to Boston this year, and it’s only a few short days away. Cadence has a demo at the Marvell booth (that’s #418-1), and we’ll be there from 3-7 PM on Wednesday, May 8 th . There, we’ll be showing off our Arm-server technology by demoing Xcelium. Be sure to stop by! Cadence and Arm have worked together to create solutions that optimize power, performance, and area while speeding up...