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Concurrent Actions in Specman

By teamspecman | 25 Mar 2019

Lately we have been asked by several customers about the concurrency options in Specman (some refer to it as “What are the Specman options similar to fork…join?”). Apparently, things that are in Specman for ages are likely to be missed. Therefore, this blog describes Specman concurrent actions (existing for years). Specman has two actions controlling concurrent execution: all of and first of. Both actions create parallel...

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first of | Specman | Specman/e | Specman e | e | specman elite
And the Winner of the 2019 DVCon U.S. Best Paper Award Is...

By XTeam | 11 Mar 2019

Another successful DVCon U.S. 2019 has come and gone, but this year had a particularly interesting highlight. With nearly 900 attendees, a bigger program of tutorials, panels, papers, and posters, and a sold-out expo, the Best Paper award was even more prestigious than ever before. This year, the award was renamed to the Stuart Sutherland Best Paper Presentation. Stu was a leading Verliog and SystemVerilog expert, and...

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DVCon 2019 | paper | Functional Verification | award
Specman is Sweet – Bosch Sensortec's Story

By XTeam | 29 Jan 2019

Recently, Bosch Sensortec has been using Specman for their functional verification needs in their Inertial Measurement Unit, and they’re loving it. Why is Specman so cool? Well, it’s implementing the familiar UVM in e, which provides the tools and infrastructure to easily build extendable, maintainable, and reusable verification components. If you use Specman, you’ll see big productivity increases. For a lot of common...

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Specman | Bosch | e | success
New Training Bytes Available Now: All About SystemVerilog Classes

By XTeam | 28 Jan 2019

If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking, don’t worry—there’s a new series of Cadence Training Bytes to help you hit the ground running in 2019. Here you’ll find eight new YouTube videos all about SystemVerilog classes. You can find the first video here . Here’s a quick table of contents: SystemVerilog Classes 1: Basics This video goes over the basics of what a SystemVerilog...

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SystemVerilog | Functional Verification | classes | training | training bytes
Verification of ML IP and Specman—Our Hackathon Project

By teamspecman | 15 Jan 2019

If you are lucky enough and your company spends a few working days each year on a Hackathon, you must know that it is usually a lot of fun. The latest 2018 Hackathon in Cadence was all about Machine Learning. We, in Specman R&D, debated a bit around how to approach the topic since Machine Learning means a lot of different things in our industry. Take a look at the following interesting article: Where ML works best in...

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ml | Specman | Specman/e | Specman e | machine learning | specman elite | verification coverage | verification
Renesas Brings Their Legacy Testbench Up to Speed Using the Cadence Verification Suite

By XTeam | 24 Dec 2018

Recently, Renesas Electronics Corporation faced a challenge. They were developing a new data conversion block, one that included an AHB bus bridge, which would be attached to a pre-existing DMA IP core. There was also a complicated finite state machine involved in this new block. Renesas didn’t have a whole lot of time on their hands—they needed a quick turnaround time, but only had a limited amount of engineers to accomplish...

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Specman | Functional Verification | Renesas | e | success
Veriest to Host Verification Meetup in Serbia Featuring Specman Macros

By Steve Brown | 30 Nov 2018

Veriest , a member of the Cadence Verification Alliance , is holding a series of Meetups in Serbia to serve the growing technology community. The December 12th event will feature a session on Specman Elite macros and how they help with reusability and maintainability. Veriest is a long time Verification Alliance member, and recently co-authored a paper with Valens on DVCon on the same topic: " Learn How Valens uses...

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Specman | veriest | specman elite | verification
Cadence Announces Full Cadence Verification Suite Compatibility for Arm-Based High Performance Computing Servers

By XTeam | 25 Oct 2018

On October 16, 2018, Cadence Design Systems, Inc announced that, through a wide-reaching system design enablement collaboration, the Cadence Verification Suite is ready for use on Arm®-based high-performance computing (HPC) server environments. Now, all of the Cadence verification software tools you know and love—including Xcelium Simulator—can be run on the Hewlett Packard Enterprise (HPE) Apollo 70 system, which uses...

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press release | HPC | ARM | announcement
Learn How Valens uses Specman Macros Automate Configuration of Verification Environments at DVCon EMEA Next Week

By Steve Brown | 16 Oct 2018

Valens has achieved success through applying Specman to their verification projects. At DVCon EMEA (Oct 24-25) you can learn how their use of Specman Macros to automate configuration of the verification environment to their design. This saves them effort and lowers the learning curve for engineers who jump from project to project. In collaboration with Veriest Verification Ltd , a Cadence Connections Verification partner...

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verification
Improving Your Testbench Flexibility with Enhanced Specman Templates

By Steve Brown | 8 Oct 2018

Cadence® Specman® Elite delivers faster and higher quality verification at block, chip, and system levels. The tool is cloud ready, supports industry-standard verification languages, and is compatible with the Open Verification Methodology (OVM), the Universal Verification Methodology (UVM), and the eReuse Methodology (eRM), so you can quickly and easily integrate it with established verification flows. Attend our...

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Specman 18.09: Avoiding the Small Annoying Mistakes

By teamspecman | 8 Oct 2018

Specman 18.09: Avoiding the Small Annoying Mistakes In almost every industry, one has the potential of making a small mistake that may cost hours or days to find. The following interesting article takes the small mistakes to the extreme and mentions a few cases of small mistakes that had a huge effect: Messing up big time: 10 tiny mistakes that have caused HUGE problems . How is it relevant to Specman? As a verification...

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enumerator | Specman | Functional Verification | e | e language | specman elite | xcelium
App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic Objects

By XTeam | 8 Oct 2018

Welcome back to the fourth installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerilog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the...

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performance | SystemVerilog | Functional Verification | xcelium simulator
Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

By XTeam | 12 Sep 2018

Join us on September 14th for a free one-hour webinar on the finer aspects of the UVM register layer. We’ll be focusing on key aspects of the UVM Register Layer that can help you with your UVM modeling in ways you may not be aware of. We’ll be covering the following topics: How to use user-defined front doors and back doors to expand what the register layer can do Understanding the role played by the predictor...

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uvm | Functional Verification | webinar | Duolos | uvm register layer
Adding a Patch Just in Time! — Or Can You Really Allow Yourself to Waste So Much Time?

By teamspecman | 30 Aug 2018

One animation video - Patch Like The Wind - is worth a thousand words :) If you don’t use Specman or don’t use Specman correctly, you spend most of your time waiting for compilation to finish. One of the most frustrating (and common…) scenarios is when you know more or less what the fix should be (such as, “wait additional cycle before sending” or “the variable should be int and not uint”) and the fix can be...

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Specman | Specman/e | Functional Verification | Specman e | tech tips | e language | team specman | save and restart
Tales From DAC: Netspeed and the Cadence Interconnect Workbench Pair Up

By XTeam | 27 Aug 2018

Services like facial detection, efficient cloud server workload management, artificial intelligence, and image enhancement are all the rage these days; but creating a design to accommodate these needs can be incredibly taxing on your engineering resources. Luckily, Netspeed Systems is here to help. The devices being designed nowadays are more complicated than ever, and the design requirements are more complex, too...

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cadence IWB | Interconnect Workbench | Functional Verification | gemini | netspeed
Tales from DAC: How Altia Systems Used Xcelium to Bring New Life to Virtual Meetings

By XTeam | 31 Jul 2018

We’re going to take a wild guess and say you’ve been in a meeting before. Maybe it was a virtual meeting—but those never really feel the same in person, do they? Attending a virtual meeting can feel cold and impersonal, especially since you can barely see everyone else. Everyone is there except you—and even then, saying you’re “there” is a bit of a stretch. Nowadays, though, there’s technology to remedy this problem...

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Functional Verification | DAC 2018 | Altia Systems | xcelium
Tales From DAC: How Syntiant Went From Zero to Tapeout in Six Months

By XTeam | 23 Jul 2018

Here’s something to chew on: Syntiant is an AI startup involved in deep learning technology and semiconductor design. Their goal is to create exceptionally low-power designs for always-on devices, like those used in speech detection. Syntiant went from empty air to tapeout in six months. That sounds hard to believe, but it’s true. They got their first venture-capital funding in October of 2017, taped out initial...

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DAC | Functional Verification | syntiant | DAC 2018 | cadence cloud
Is it Time to Verify Your Chips in the Cloud? Part 3 of 3

By XTeam | 28 Jun 2018

Welcome back to our series on cloud verification solutions. This is the final part of a three-part blog—you can read part one here and part two here . Now, for the moment you’ve all been waiting for: what can Cadence do for you in the realm of cloud verification. Are you ready? In case you saw that list of qualities one should look for in a cloud partner in the last part of this blog, and wondered who ticks all those...

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security | Functional Verification | cadence cloud | xcelium | palladium cloud
UVM-ML- Managers’ Freedom of Choice

By teamspecman | 28 Jun 2018

Freedom of choice is a term we hear a lot, especially in the last 10 years. It is defined in wikipedia as “an individual's opportunity and autonomy to perform an action selected from at least two available options…”. Is having many choices always a good thing? Well, usually it is- who would not want to live in a world where s/he has options and can make choices? However, there are also downsides to having multiple...

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Specman | Specman/e | UVM-ML | Specman e | UVM multi-language | UVM-e | UVM ML | multi-language | multi-language UVM | multi-language verification | verification
Is It Time to Verify Your Chips in the Cloud? Part 2 of 3

By XTeam | 21 Jun 2018

Welcome back to our series on cloud verification solutions. This is part two of a three-part blog—you can read part one here . The high-performance computing (HPC) market continues to grow. Analysts say that the HPC market will reach almost $11 billion by 2020—that’s an annual growth rate of almost 20%. Cloud providers and other related companies are putting more and more resources into building solutions for this...

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uvm | Functional Verification | EDA | HPC | cadence cloud
App Note Spotlight: Streamline Your SystemVerilog Code, Part III - SystemVerilog Data Structures

By XTeam | 21 Jun 2018

Welcome back to the third installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked— Simulation Performance Coding Guidelines for SystemVerilog . This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium...

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SystemVerilog | Tip | Functional Verification | App Note Spotlight
Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

By XTeam | 15 Jun 2018

Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud. For a while now, there’s been a growing interest in cloud-based EDA solutions, but the time wasn’t ripe for production deployment. People had concerns about security and the sustainability of the data centers. But nowadays, public clouds are highly secure, typically more secure...

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cloud-based verification | Functional Verification | cadence cloud | cloud computing
DMS 2.0 - What's Cool and What's New

By XTeam | 11 Jun 2018

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)? Provided with the Xcelium Parallel Simulator versions 17.10 and beyond, DMS 2.0 brings you all kinds of new and wonderful features to help you use Xcelium to verify your mixed-signal designs. The level of interaction between analog structures and digital logic is a lot more complex than it used to be. Divide-and-conquer verification isn...

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digital mixed signal | Functional Verification | DMS 2.0 | xcelium simulator
Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load

By XTeam | 7 Jun 2018

Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic Test Load for some time now, and they shared their thoughts on it in a paper presented at CDNLive San Jose April 2018. One of the fields Microsemi operates in is the realm of optical networking. In optics, a given sensor’s input can vary wildly, but the way the input is processed is largely the same. Thus, a wide variety of tests are...

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SystemVerilog | uvm | Dynamic Test Load | Functional Verification | xcelium
RAK Attack: Verifying Power Intent for Low Power Mixed Signal SoCs

By XTeam | 5 Jun 2018

The wait is finally over—the Rapid Adoption Kit (RAK) for verifying the power intent of low-power mixed signal SoCs is here! The RAK is a tutorial designed to clearly show, through example, how to verify one of the most critical technology convergences in IoT devices. It’ll talk about the differences in verification of a processor-based design whether it’s powered internally or externally, how to verify SPICE, SystemVerilog...

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Low Power | Functional Verification | RAK | power intent | mixed signal

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