Featured

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

What Does EDA360 Mean for Verification Engineers?

I trust that most of you have seen the recent flurry of blog posts and articles about…

• 2 min read
uvm , IP , Verification methodology , OVM , VIP , EDA360

System Realization activities at CDNLive! EMEA this week

CDNLive! EMEA will be held in Munich again this year, and there’s lots of news about…

• 2 min read
System Design and Verification , cdnLive! system realization

See You at CDNLive! EMEA

Today, Team Specman reported that next week's CDNLive! is shaping up to be a big…

• 2 min read
CDNLive!ive! , System Design and Verification

2010 CDNLive Munich Guide for Specmaniacs

Good news for Specmaniacs based in the EU: next week from May 4-6 is the annual CDNLive…

• 2 min read
Specman , CDNLive , Functional Verification , Cadence VIP portfolio , OVM , OVM e , e , Mike Stellfox , techtorial

Team Verify's 2010 CDNLive Munich Guide

We're excited to report that next week's annual CDNLive! event in Munich will feature…

• 1 min read
ABV , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Contributions , SVA , PSL , MDV , IEV , IFV

Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%

More and more often it takes a village to achieve verification success. As reported…

• 1 min read
Functional Verification , Incisive , xilinx , IES , FPGA , Matlab , IES-XL

Verified by e/Specman: The Palladium XP Verification Computing Platform

After much anticipation, it feels great to be free to proclaim that e /Specman (as…

• less than a min read
metric driven verification (MDV) , Functional Verification , e , Palladium XP , MDV , IES-XL

Ubuntu on ARM is Growing

Based on the title, you probably guessed I'm talking about growing in popularity…

• 6 min read
virtual platform , System Design & Verification , Embedded Linux , QEMU

UVM Based on OVM 2.1.1: What a Great Idea!

Regular readers know that I have been urging the Accellera VIP TSC to base its Universal…

• 2 min read
uvm , Verification methodology , OVM , Functional Verification' signal integrity , Contributions , Accellera

When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog…

Building on the packet generation example of part 1 , and the coverage examples of…

• 3 min read
IEEE 1647 , SystemVerilog , Specman , Object Oriented Programming , Functional Verification , e , OOP , Aspect Oriented Programming , AOP , IES-XL

Specman-SimVision webinar on April 22 (next week!)

We interrupt Corey's excellent "When Less Is More" series to announce a Specman-SimVision…

• 1 min read
IEEE 1647 , debug , Functional Verification , simvision , e , multi-language , IES-XL

Hate Writing Assertions? No problem: let Automatic Formal Analysis do the work

OR: “Leverage automatic checks extracted from designs without writing a single assertion…

• 4 min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

New Blog: All About Integrated formal, Simulation, and Assertion-Based Verification…

End-users of Incisive Formal Verifier ("IFV"), Incisive Enterprise Verifier ("IEV…

• 1 min read
ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , OVM , Incisive , Twitter , MDV , IEV , IFV

When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog…

In my last post I wrote some packet generation code to validate the claim that e…

• 4 min read
IEEE 1647 , SystemVerilog , Functional Verification , OVM , OVM e , CDV , OVM SV , e , coverage driven verification (CDV) , Aspect Oriented Programming , AOP , IES-XL

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines…

• 3 min read
IEEE 1647 , SystemVerilog , Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , e , OOP , ClubT , Aspect Oriented Programming , AOP , IES-XL

Accessing Physical Memory and Registers in a Virtual World

When working with Virtual Platforms that are running operating systems it's sometimes…

• 3 min read
Registers , Memory , virtual platforms , Virtual , System Design and Verification

Tweeting From a Standards Meeting: Good or Bad?

In my last blog entry , I mentioned that I was able to keep up with a lot of the…

• 2 min read
uvm , tweeting , meetings , Functional Verification , texting , Accellera , EMAIL

Free eVC Generator From CFS Vision Update

In an earlier post Team Specman had the pleasure of introducing the free, open source…

• less than a min read
Specman , Functional Verification , OVM e , e , CFS Vision , FOSS , eRM

Crises In The Semiconductor Industry

I am on my way to Japan and I have just finished to read an excellent book and in…

• 2 min read
System Design and Verification , SoC , Semiconductor , ESL

Built-in Message Logging – Part 2 of 2

[Team Specman welcomes back guest blogger, Michael Avery from our Services Group…

• 3 min read
Specman , debug , Functional Verification , e , Funcional Verification , Aspect Oriented Programming , AOP

UVM = OVM 2.1: Even Better!

Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face…

• 1 min read
uvm , Functional Verification , OVM , Accellera VIP TSC

Built-in Message Logging – Part 1 of 2

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the…

• 2 min read
Specman , Functional Verification , tech tips , e , AOP , IES-XL

VIP Portfolio Extension: New AMBA 4 Protocol Support

ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing…

• 1 min read
metric driven verification (MDV) , Functional Verification , vPlan , Cadence VIP portfolio , OVM , VIP , Compliance Management System , CMS , AMBA , ARM

Have You Considered e Lately?

Richard Goering's recent interview with Mitch Weaver on the future of Specman and…

• 2 min read
SystemVerilog , Specman , Testbench simulation , e , verification

Running Incisive on Ubuntu Linux

Ubuntu is by many accounts the most popular and the easiest to use Linux distribution…

• 4 min read
Incisive , Ubuntu , Systemm Design and Verification , Virtual Machine , linux

Why OOP Falls Short For Verification

Last week at DVCon , frequent Team Specman guest blogger Matan Vax of R&D gave a…

• less than a min read
Object Oriented Programming , Functional Verification , e , DVcon , OOP , Aspect Oriented Programming , AOP

DVCon 2010 - Day 3

Click here or on the image below to go to the annotated photo blog of DVCon 2010…

• less than a min read
Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , DVcon , OOP , AMIQ , OVM SC

DVCon 2010 Rocked!

I've spent much of this week at the San Jose Doubletree Hotel for DVCon 2010 , and…

• 1 min read
DAC , uvm , methodology , Functional Verification , OVM , DVcon
Blog - Title