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Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Training Insights - Still Relying on Static-Only CDC Signoff? Introducing the JasperGold…

RTL designers are creating increasingly complex designs, and are under relentless…

• 3 min read
Functional Verification , clock domain crossings , CDC , RDC , JasperGold , Superlint , Reset , Formal verification

Have You Ever Wanted to Learn Specman/e and Did Not Know How?

As a verification engineer, you want your toolbox to be varied and rich. It looks…

• 1 min read
Specman , Specman/e , Functional Verification , hvl

Ouch that’s Hot! Register Access Heatmap

We’re proud to see that many expert verification teams exploit the powers of UVM…

• 1 min read
Specman , Specman e , vr_ad , specman elite

Renesas Sees Success With the Full System Solution

If you’re looking for an example of how well the Cadence flow fits together, look…

• 2 min read
iwb , Perspec , Palladium , Renesas , system performance analyzer , system testbench generator

JasperGold FPV: Asynchronous Designs? No Problem!

Asynchronous designs happen. They’re not particularly easy to verify, but sometimes…

• 1 min read
Functional Verification , jaspergold fpv , asynchronous , JasperGold

Cadence Is Arm-and-Arm with Arm: Fast Models for Fast Prototyping

If you’re not familiar with the Arm/Cadence collaboration , you’ve been missing out…

• 1 min read
Fast Models , Protium , Palladium , ARM

Celsius on Protium - Using Cadence Tools to Improve Cadence Tools?

The Cadence tool flow is the most comprehensive flow around. If there is an EDA need…

• 1 min read
celsius , Functional Verification , Protium

Mellanox's Tips and Tricks for Maximizing Your Palladium Unit

Looking to learn more about the best practices for emulating today’s billion-gate…

• 1 min read
Functional Verification , mellanox , Palladium , Tips

Xcelium ML: The Next Big Thing in Regression

Looking for that extra kick in your regression performance? Cadence’s Xcelium Logic…

• 1 min read
machine learning , xcelium , Regression

The Best Way to Learn SystemVerilog Accelerated Verification with UVM – Blended …

UVM is a heavily used, standard, proven, easy-to-use, automated verification methodology…

• 3 min read
online_training , uvm , blended_training , training_bytes , digital_badge , Cadence support

Troubleshooting Xcelium Errors/Warnings with xmhelp/xmbrowse and Cadence Support…

I joined Cadence in July 2000 and was immediately put on a three-month training to…

• 4 min read
extended help , incisive utility nchelp , nchelp , troubleshooting xcelium errors , xcelium error extended help , incisive error extended help , xmhelp

Improving Tests Efficiency Using Coverage Callback (part 2)

In recent blogs - specman-callback-coverage-api and improving-tests-efficiency-using…

• 3 min read
Specman , Functional Verification , Coverage-Driven Verification , e , e language

Training Insights - Comprehensive RTL Signoff Using JasperGold Superlint App

Most have heard the phrase "time is money". Thinking more about it, probably the…

• 2 min read
Functional Verification , bugs , RTL , formal , RTL designer Signoff , webinar , assertions , Lint , Superlint

Improving Tests Efficiency Using Coverage Callback

When you go to the store, you walk until you get there, stop, get your groceries…

• 7 min read
Specman , coverage , Functional Verification , Specman e , Coverage-Driven Verification , e , verification

Interconnect Beyond PCIe: CXL and Cache Coherent Interconnect

As the de facto IO interconnect technology, PCIe has commendably addressed the performance…

• 2 min read
Verification IP , VIP , PCIe , Internet of Things , Denali , PCI Express , verification

Catching up with Higher Ethernet Speed: VIP Supports 802.3ck

Draft 1.0 of 802.3ck, also known as 100G per lane, was finally published by IEEE…

• 2 min read
802.3ck , Ethernet VIP , baseR , VIP , 100Gbps , 100G backplane , CGPL

Sizing Up eUSB2 Verification

USB is one of the most widely used interfaces in the PC market for more than 20 years…

• 2 min read
VIP , USB-IF , eUSB , USB 2.0 , eUSB2

Why Is the Evolving HBM3 Such a Revolutionary Technology and How Can You Be Ready…

Since 2013, we have seen the HBM specifications being released by JEDEC and companies…

• 3 min read
Verification IP , Memory , VIP , JEDEC , HBM , storage , Design IP and Verification IP , verification

Specman’s Callback Coverage API

Our customers’ tests have become more complex, longer, and consume more resources…

• 5 min read
Specman , Specman/e , Specman coverage engine , coverage , Specman e , specman elite , Coverage Driven Verification

Metamorphic Testing: The Future of Verification?

Curious about what’s going on behind the scenes with verification? Bernard Murphy…

• 1 min read
Functional Verification , Semiwiki , metamorphic testing

RAK Attack: Better Driver Tracing, Faster Palladium Build Time, UVM Register Map…

Looking to learn? There's a bunch of new RAKs (Rapid Adoption Kits) available online…

• 2 min read
Rapid Adoption Kit , IXCOM , RAK , Indago , JasperGold

Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple

Verifying lane adapter state machine in a router design is quite an involved task…

• 1 min read
Verification IP , DP , VIP , DisplayPort , PCIExpress , USB , Lane Adapter , usb4 , PCIe , usb4 router , tunneling

A Specman/e Syntax for Sublime Text 3

We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab…

• 1 min read
Specman , Specman/e , Specman e , Sublime Text , specman elite

USB3, PCIe, DisplayPort Protocol Traffic Finding its Way Through USB4 Routers

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic…

• 1 min read
Verification IP , DP , DisplayPort , USB , usb4 , PCIe , tunneling

Cashing the PSS Promises

A little bit of everything in the blog today: PSS is All Over As someone that was…

• 1 min read
uvm , CDNLive , Acceleration , virtual prototypes , Perspec , perspec system verifier , Emulation , DVcon , Accellera , System Design & Verification , pss , portable stimulus , verification

Specman: Analyze Your Coverage with Python

In the former blog about Python and Specman: Specman: Python Is here! , we described…

• 8 min read
Specman , Specman coverage engine , coverage , Python , Functional Verification , Specman e , e , e language , specman elite , functional coverage

Dimensions to Verifying a USB4 Design

Verification of a USB4 router design is not just about USB4 but also about the inclusion…

• 2 min read
Verification IP , Router , DisplayPort , USB , usb4 , PCIe , USB3 , tunneling

Automotive Security in the World of Tomorrow - Part 2 of 2

If you missed the first part of this series, you can find it here . So: what does…

• 2 min read
security , Automotive , Functional Verification , Green Hills Software
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