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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

UVM-ML- Managers’ Freedom of Choice

Freedom of choice is a term we hear a lot, especially in the last 10 years. It is…

• 5 min read
Specman , Specman/e , UVM-ML , Specman e , UVM multi-language , UVM-e , UVM ML , multi-language , multi-language UVM , multi-language verification , verification

Is It Time to Verify Your Chips in the Cloud? Part 2 of 3

Welcome back to our series on cloud verification solutions. This is part two of a…

• 1 min read
uvm , Functional Verification , EDA , HPC , cadence cloud

App Note Spotlight: Streamline Your SystemVerilog Code, Part III - SystemVerilog…

Welcome back to the third installment of a special multi-part edition of the App…

• 2 min read
SystemVerilog , Tip , Functional Verification , App Note Spotlight

Is it Time to Verify Your Chips in the Cloud? Part 1 of 3

Welcome to the first installment of a three-part blog series examining the issues…

• 2 min read
cloud-based verification , Functional Verification , cadence cloud , cloud computing

DMS 2.0 - What's Cool and What's New

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)…

• 1 min read
digital mixed signal , Functional Verification , DMS 2.0 , xcelium simulator

Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load

Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic…

• 2 min read
SystemVerilog , uvm , Dynamic Test Load , Functional Verification , xcelium

PCI-SIG Developer's Conference: What's New with Gen 5 and When Will it be Adopted…

The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement…

• 3 min read
controller IP , Verification IP , PCIe Gen4 , PHY , PCIe , PCIe Gen5 , verification

RAK Attack: Verifying Power Intent for Low Power Mixed Signal SoCs

The wait is finally over—the Rapid Adoption Kit (RAK) for verifying the power intent…

• 2 min read
Low Power , Functional Verification , RAK , power intent , mixed signal

App Note Spotlight: Streamline Your SystemVerilog Code, Part II - SystemVerilog …

Welcome back to a special multi-part edition of the App Note Spotlight, where we…

• 2 min read
performance , SystemVerilog , Functional Verification , xcelium simulator

Empowering Generation - Range Generated Fields (RGF)

Specman constraints solver process consists of a series of reductions and assignments…

• 8 min read
Specman , Specman/e , Generation , e language , Constraints

Leading the Charge: Cadence Announces New Verification IP for UFS 3.0, CoaxPress…

Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence…

• 1 min read
hyperRAM , Functional Verification , coaxpress , UFS , press release

How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a Preliminary…

We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary…

• 2 min read
DDR Controller , Verification IP , ddr5 , DDR4 , TSMC Tech Symposium , TSMC , DDR , DDR PHY

Xcelium's New Save and Restart Saves You Time

You may have heard about the overhaul to the old save/restart mechanism that was…

• 2 min read
save and restart , xcelium , save and restore , checkpointing

New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP

As discussed in the previous installments of the blog, the recent update of the AMBA…

• 3 min read
amba5 , Verification IP , ACE VIP , AXI VIP , AMBA

NVMe Express 1.3: Addressing the Storage Needs of the Data Revolution from Enterprise…

The amount of data we are generating and consuming has exploded in recent years.…

• 2 min read
Verification IP , NVM Express , NVMe , IoT , VIP , cloud , big data , storage , PCIe , PCI Express , data centers

List of TLM Analysis Ports: Where Is This Packet Coming From?

Let’s say that you got an invitation from the police station nearest your home to…

• 4 min read
Specman , Functional Verification , e , e language , team specman , xcelium

What’s Hot in Verification at this Year’s CDNLive? It’s Portable Stimulus Again!

CDNLive is a user conference, and verification is one of the largest categories of…

• 2 min read
CDNLive , Perspec , pss , portable stimulus

App Note Spotlight: Streamline Your SystemVerilog Code, Part I

Welcome to a special multi-part edition of the App Note Spotlight, where we’ll be…

• 2 min read
SystemVerilog , Object Oriented Programming , Functional Verification , Optimize

Preparing Accellera Portable Stimulus Standard for Ratification

The Accellera Portable Stimulus Working Group met at the DVCon 2018 to move the process…

• less than a min read
pswg , Perspec , perspec system verifier , pss , portable stimulus

Temporals, Reset, and Test Phases

One of the biggest challenges in dynamic functional verification is testing Reset…

• 4 min read
Specman , UVM e , Specman e , e , e language

App Note Spotlight: Choosing the Incremental Elaboration Flow That’s Right For Y…

Welcome to another App Note Spotlight! One of the biggest issues facing verification…

• 2 min read
incremental elaboration , Flows , Functional Verification , MSIE

Xcelium and Cavium: What’s the Deal?

So—you may have heard that Xcelium Parallel Simulator is available on Arm servers…

• 1 min read
thunder x2 , video , Cavium , xcelium

New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

As discussed in the previous installment of this blog, a new class of atomic transactions…

• 1 min read
amba5 , ACE5 , AXI5 , Atomic Transactions

Coming to DVCon? It's Not Too Late to Sign Up!

Are you coming to DVCon this year? It’s right around the corner, but it’s not too…

• 1 min read
Functional Verification , DVcon 2018 , tutorials , event

New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions

The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant…

• 2 min read
amba5 , ACE5 , AXI5 , AMBA

JEDEC UFS 3.0 Now Available in Cadence VIP Portfolio – For Mobile and Automotive…

The JEDEC UFS (Universal Flash Storage) started in 2011 with the v1.0 first specification…

• 1 min read
Verification IP , UniPro , MIPI Alliance , JEDEC , automotive electronics , UFS , storage , MPHY

Type MIN / MAX Values in Specman

When defining coverage bins for coverage items, the number and size of bins depend…

• 3 min read
Specman , Specman coverage engine , Specman e

App Note Spotlight: SystemVerilog Gets a Real Number Modeling Update (SVRNM)

Thanks to Xcelium, there’s a new feature on the block in SystemVerilog. It pertains…

• 1 min read
SystemVerilog , real number modeling , Functional Verification , App Note Spotlight
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