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Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

From AMBA ACE to CHI, Why Move for Coherency?

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from existing AXI protocol…

• 2 min read
Verification IP , ACE VIP , Functional Verification , VIP , coherency , CHI VIP

Why is Ethernet Time-sensitive Networking (TSN) Adaptation So Rapid in the Automotive…

At a particular point in time, the automotive industry continued to add more and…

• 1 min read
Automotive , Verification IP , SoC verification , IP verification , Ethernet VIP , Functional Verification , VIP , Ethernet standards , Automotive Ethernet , TSN

Single DRAM or Multi-DRAMs Memory Sub-system for Your Next SOC ?

Even with the DRAM capacity going up with each generation of DRAM, the demand for…

• 2 min read
Verification IP , ddr5 , Memory , DDR5 DIMM , JEDEC , lpddr5 , MMAV

Verification of Integrity and Data Encryption(IDE) for PCIe Devices

The concept of Trusted Execution Environments (TEE) was developed in the early 2000s…

• 4 min read
security , funtional verification , pcie 5 , PCIExpress , encryption , PCIe , pcie gen6 , IDE

Training Insights - Addressing Security Verification Requirements with JasperGold…

As a chip designer, you’re probably spending as much headspace on security threats…

• 2 min read
online , CDC , training , app , JasperGold , verification

Comprehensive Approach to Verification of Interconnect-Centric Systems

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP…

• 2 min read
interconnect , scoreboard , SoC verification , Functional Verification

Why IDE Security Technology for PCIe and CXL?

The new cloud, AI, Analytics, and Edge usage models with exponential data growth…

• 3 min read
Verification IP , Functional Verification , VIP , System Verification , simulation , verification

PIPE SerDes Architecture for PCIe Gen 5 and Beyond

Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification…

• 2 min read
Intel , IP verification , PHY , pcie 5 , VIP , PCIe , SerDes , pcie gen6

Training Insights — Metastability-Aware Verification: Elevate Your Signoff with JasperGold…

I hope you enjoyed and got good insights about the Cadence® JasperGold® CDC during…

• 2 min read
CDC , RTL designer Signoff , Metastability , JasperGold , verification

Webinar: Using e Reflection

Join Cadence Training and Software Architect Efrat Shneydor for this free technical…

• 1 min read
Specman , Specman e , training , webinar , reflection

AMBA 5 ACE/AXI Specification Updates and Their Support in Cadence ACE/AXI VIP

As discussed in the previous blog, the AMBA® 5 specification updates introduced several…

• 3 min read
amba5 , ACE5 , AXI5 , Funcional Verification , AMBA Verification IP , System Verification Scoreboard

How to Verify LPDDR5 from IP to System Level?

LPDDR5 DRAM aims to serve a wide array of markets, including automotive, client PCs…

• 3 min read
Verification IP , SoC verification , Specman , Memory , Functional Verification , VIP , JEDEC , Memory Model Portfolio , storage , lpddr5 , lpddr5x

Introduction to Macros – Answers to Your Questions

Thanks to all the people who attended the webinar Extend the Language! An Introduction…

• 5 min read
Specman , Functional Verification , e , webinar , training bytes , macro debugging , e language , macros

What Disruptive Changes to Expect from PCI Express Gen 6.0

PCIe (Peripheral Component Interconnect Express) has long been the backbone of complex…

• 3 min read
SoC verification , Functional Verification , Modeling , verification

What Is New in the Latest AMBA 5 ACE, AXI and AHB Protocol Specification Updates…

The industry-standard ARM AMBA® 5 protocol specifications continue to evolve, further…

• 1 min read
amba5 , Functional Verification , ACE5 , AXI5 , AMBA VIP , AMBA Verification IP , AHB5

PSS2.0 is Out – Reflections on the Role of a Standard

We all know that a common language is the basis for every collaborative activity…

• 3 min read
portable test and stimulus standard , standardization , pss2.0 , pss

CCIX Coherency: Verification Challenges and Approaches

Cache coherency is not a new concept. Coherent architectures have existed for many…

• 2 min read
SoC verification , ccix , PCIe , coherency , CXS

PSS 2.0 Is Available and Driving Portable Stimulus to the Mainstream!

Three years ago, PSS (Portable Test and Stimulus) specification 1.0 was released…

• 2 min read
Perspec , pss , portable stimulus , verification

TileLink: Chip-Scale Cache-Coherent Interconnect Protocol

RISC-V, an open specification of an Instruction Set Architecture (ISA), which was…

• 1 min read
TileLink , Verification IP , risc-v , VIP , cache coherency

Verifying Protocol Tunneling with Cadence USB4 VIP — The Multiprotocol Advantage

All the workings of USB4 protocol are primarily about how to transfer the native…

• 1 min read
Verification IP , USB4 VIP , DisplayPort , usb4 , PCIe , Protocol Tunneling , usb4 router , USB3

Transport Layer – The Backbone of a USB4 Router

It won’t be incorrect to say that the transport layer of a USB4 router is the backbone…

• 1 min read
Verification IP , USB4 VIP , usb4 , usb4 router

Webinar: Extend the Language Using Specman e Macros!

Using Cadence ® Specman ® Elite macros lets you extend the e language ─ i.e. invent…

• 1 min read
Specman , e , training , webinar , macros

Taking LPDDR5 to the Next Level

To cater to ever-increasing bandwidth demands from low-power DRAMs especially for…

• 2 min read
Verification IP , Memory , VIP , JEDEC , lpddr5 , lpddr5x

DisplayPort 128b/132b Concurrent LTTPR Link Training

Before a video frame can be sent, the Source (DP-TX) must complete link training…

• 1 min read
Verification IP , DisplayPort , TripleCheck

HyperRam as DRAM for Some Applications!!!

Applications like Automotive, Industrial control panels, Smart Home, Smart watches…

• 1 min read
Verification IP , hyperRAM , Memory , VIP , HyperBus , verification

Training Insights - Clean RTL Faster Without Simulation! Here’s How.

RTL designers are challenged by increasingly complex designs. They’re also expected…

• 2 min read
Functional Verification , RTL , webinar , JasperGold

Higher FLASH Throughput for Your Next SoC Design

Memory is an important part of every electronic system, still it is increasingly…

• 1 min read
Verification IP , Memory , flash , VIP , JEDEC , storage

Xcelium Provides 3X Performance Increase for StreamDSP's FPGA-Based Defense IP

The FPGA market is rapidly growing in the traditional Aero-Defense sector as well…

• 3 min read
A&D , performance , Functional Verification , simvision , cadenceconnect , regression throughput , xcelium simulator , aero-defense , JasperGold , FPGA
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