Featured

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus
Verification
Latest blogs

TileLink: Chip-Scale Cache-Coherent Interconnect Protocol

RISC-V, an open specification of an Instruction Set Architecture (ISA), which was…

• 1 min read
TileLink , Verification IP , risc-v , VIP , cache coherency

Verifying Protocol Tunneling with Cadence USB4 VIP — The Multiprotocol Advantage

All the workings of USB4 protocol are primarily about how to transfer the native…

• 1 min read
Verification IP , USB4 VIP , DisplayPort , usb4 , PCIe , Protocol Tunneling , usb4 router , USB3

Transport Layer – The Backbone of a USB4 Router

It won’t be incorrect to say that the transport layer of a USB4 router is the backbone…

• 1 min read
Verification IP , USB4 VIP , usb4 , usb4 router

Webinar: Extend the Language Using Specman e Macros!

Using Cadence ® Specman ® Elite macros lets you extend the e language ─ i.e. invent…

• 1 min read
Specman , e , training , webinar , macros

Taking LPDDR5 to the Next Level

To cater to ever-increasing bandwidth demands from low-power DRAMs especially for…

• 2 min read
Verification IP , Memory , VIP , JEDEC , lpddr5 , lpddr5x

DisplayPort 128b/132b Concurrent LTTPR Link Training

Before a video frame can be sent, the Source (DP-TX) must complete link training…

• 1 min read
Verification IP , DisplayPort , TripleCheck

HyperRam as DRAM for Some Applications!!!

Applications like Automotive, Industrial control panels, Smart Home, Smart watches…

• 1 min read
Verification IP , hyperRAM , Memory , VIP , HyperBus , verification

Training Insights - Clean RTL Faster Without Simulation! Here’s How.

RTL designers are challenged by increasingly complex designs. They’re also expected…

• 2 min read
Functional Verification , RTL , webinar , JasperGold

Higher FLASH Throughput for Your Next SoC Design

Memory is an important part of every electronic system, still it is increasingly…

• 1 min read
Verification IP , Memory , flash , VIP , JEDEC , storage

Xcelium Provides 3X Performance Increase for StreamDSP's FPGA-Based Defense IP

The FPGA market is rapidly growing in the traditional Aero-Defense sector as well…

• 3 min read
A&D , performance , Functional Verification , simvision , cadenceconnect , regression throughput , xcelium simulator , aero-defense , JasperGold , FPGA

Training Insights - Still Relying on Static-Only CDC Signoff? Introducing the JasperGold…

RTL designers are creating increasingly complex designs, and are under relentless…

• 3 min read
Functional Verification , clock domain crossings , CDC , RDC , JasperGold , Superlint , Reset , Formal verification

Have You Ever Wanted to Learn Specman/e and Did Not Know How?

As a verification engineer, you want your toolbox to be varied and rich. It looks…

• 1 min read
Specman , Specman/e , Functional Verification , hvl

Ouch that’s Hot! Register Access Heatmap

We’re proud to see that many expert verification teams exploit the powers of UVM…

• 1 min read
Specman , Specman e , vr_ad , specman elite

Renesas Sees Success With the Full System Solution

If you’re looking for an example of how well the Cadence flow fits together, look…

• 2 min read
iwb , Perspec , Palladium , Renesas , system performance analyzer , system testbench generator

JasperGold FPV: Asynchronous Designs? No Problem!

Asynchronous designs happen. They’re not particularly easy to verify, but sometimes…

• 1 min read
Functional Verification , jaspergold fpv , asynchronous , JasperGold

Cadence Is Arm-and-Arm with Arm: Fast Models for Fast Prototyping

If you’re not familiar with the Arm/Cadence collaboration , you’ve been missing out…

• 1 min read
Fast Models , Protium , Palladium , ARM

Celsius on Protium - Using Cadence Tools to Improve Cadence Tools?

The Cadence tool flow is the most comprehensive flow around. If there is an EDA need…

• 1 min read
celsius , Functional Verification , Protium

Mellanox's Tips and Tricks for Maximizing Your Palladium Unit

Looking to learn more about the best practices for emulating today’s billion-gate…

• 1 min read
Functional Verification , mellanox , Palladium , Tips

Xcelium ML: The Next Big Thing in Regression

Looking for that extra kick in your regression performance? Cadence’s Xcelium Logic…

• 1 min read
machine learning , xcelium , Regression

The Best Way to Learn SystemVerilog Accelerated Verification with UVM – Blended …

UVM is a heavily used, standard, proven, easy-to-use, automated verification methodology…

• 3 min read
online_training , uvm , blended_training , training_bytes , digital_badge , Cadence support

Troubleshooting Xcelium Errors/Warnings with xmhelp/xmbrowse and Cadence Support…

I joined Cadence in July 2000 and was immediately put on a three-month training to…

• 4 min read
extended help , incisive utility nchelp , nchelp , troubleshooting xcelium errors , xcelium error extended help , incisive error extended help , xmhelp

Improving Tests Efficiency Using Coverage Callback (part 2)

In recent blogs - specman-callback-coverage-api and improving-tests-efficiency-using…

• 3 min read
Specman , Functional Verification , Coverage-Driven Verification , e , e language

Training Insights - Comprehensive RTL Signoff Using JasperGold Superlint App

Most have heard the phrase "time is money". Thinking more about it, probably the…

• 2 min read
Functional Verification , bugs , RTL , formal , RTL designer Signoff , webinar , assertions , Lint , Superlint

Improving Tests Efficiency Using Coverage Callback

When you go to the store, you walk until you get there, stop, get your groceries…

• 7 min read
Specman , coverage , Functional Verification , Specman e , Coverage-Driven Verification , e , verification

Interconnect Beyond PCIe: CXL and Cache Coherent Interconnect

As the de facto IO interconnect technology, PCIe has commendably addressed the performance…

• 2 min read
Verification IP , VIP , PCIe , Internet of Things , Denali , PCI Express , verification

Catching up with Higher Ethernet Speed: VIP Supports 802.3ck

Draft 1.0 of 802.3ck, also known as 100G per lane, was finally published by IEEE…

• 2 min read
802.3ck , Ethernet VIP , baseR , VIP , 100Gbps , 100G backplane , CGPL

Sizing Up eUSB2 Verification

USB is one of the most widely used interfaces in the PC market for more than 20 years…

• 2 min read
VIP , USB-IF , eUSB , USB 2.0 , eUSB2

Why Is the Evolving HBM3 Such a Revolutionary Technology and How Can You Be Ready…

Since 2013, we have seen the HBM specifications being released by JEDEC and companies…

• 3 min read
Verification IP , Memory , VIP , JEDEC , HBM , storage , Design IP and Verification IP , verification
Blog - Title