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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Thinci Finds Success with the Cadence Verification Suite

On May 23rd, 2019, Cadence announced that Thinci has elected to use the complete…

• 1 min read
ThinCi , Functional Verification , cadence verification suite , success story , verification

Concurrent Actions in Specman: Part 2

In the previous blog: Concurrent Actions in Specman , we discussed the existing options…

• 4 min read
Specman , Specman/e , Specman e , concurrency , specman elite

Cadence at the Red Hat Summit--Come See Xcelium in Action!

The Red Hat Summit is coming around to Boston this year, and it’s only a few short…

• less than a min read
Functional Verification , red hat summit , xcelium , event

Cadence at the HOST Symposium: Come See What We're Doing!

The HOST Symposium is returning for its 12 th year, and general registration is open…

• 1 min read
host , Functional Verification , symposium , event

Specman Linting and the all_unique Method

Sorting according to pointers- why? One of the best practices that you need to…

• 4 min read

Cadence Announces Continued Partnership With Northrop Grumman

On March 28th, 2019, Cadence Design Systems announced an expanded collaboration with…

• 1 min read
chip design , Functional Verification , press release , Northrop Grumman

Cadence Leads the Pack: The First VIP for USB4 is Here!

On March 14th, Cadence announced the release of the industry’s first USB4-supporting…

• 1 min read
Functional Verification , VIP , usb4 , press release

Concurrent Actions in Specman

Lately we have been asked by several customers about the concurrency options in Specman…

• 2 min read
first of , Specman , Specman/e , Specman e , e , specman elite

NVMe 2019 Developer's Conference: NVMe 1.4 Is Almost Here, and Enterprise and Cloud…

Unlike previous years, the annual NVM Express Developer’s Conference was held in…

• 2 min read
Verification IP , Enterprise , NVM Express , PCIe Gen4 , NVMe , VIP , cloud , PCIe , PCI Express , TripleCheck

And the Winner of the 2019 DVCon U.S. Best Paper Award Is...

Another successful DVCon U.S. 2019 has come and gone, but this year had a particularly…

• 1 min read
DVCon 2019 , paper , Functional Verification , award

Specman is Sweet – Bosch Sensortec's Story

Recently, Bosch Sensortec has been using Specman for their functional verification…

• 1 min read
Specman , Bosch , e , success

New Training Bytes Available Now: All About SystemVerilog Classes

If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking…

• 2 min read
SystemVerilog , Functional Verification , classes , training , training bytes

Verification of ML IP and Specman—Our Hackathon Project

If you are lucky enough and your company spends a few working days each year on a…

• 7 min read
ml , Specman , Specman/e , Specman e , machine learning , specman elite , verification coverage , verification

Renesas Brings Their Legacy Testbench Up to Speed Using the Cadence Verification…

Recently, Renesas Electronics Corporation faced a challenge. They were developing…

• 1 min read
Specman , Functional Verification , Renesas , e , success

Verification Reflections on 2018

In my predictions for 2018 I had identified five key trends driving verification…

• 5 min read
security , functional safety , verification

Willamette HDL and Cadence Develop the Industry's First PSS Training Course for Perspec…

Cadence continues to be a leader in SoC verification and has expanded our industry…

• 1 min read
whdl , Perspec , perspec system verifier , willamette hdl , Accellera , pss , portable stimulus , Accellera PSS

Veriest to Host Verification Meetup in Serbia Featuring Specman Macros

Veriest , a member of the Cadence Verification Alliance , is holding a series of…

• less than a min read
Specman , veriest , specman elite , verification

Cadence Announces Full Cadence Verification Suite Compatibility for Arm-Based High…

On October 16, 2018, Cadence Design Systems, Inc announced that, through a wide-reaching…

• 1 min read
press release , HPC , ARM , announcement

Learn How Valens uses Specman Macros Automate Configuration of Verification Environments…

Valens has achieved success through applying Specman to their verification projects…

• less than a min read
verification

Improving Your Testbench Flexibility with Enhanced Specman Templates

Cadence® Specman® Elite delivers faster and higher quality verification at block…

• less than a min read

Specman 18.09: Avoiding the Small Annoying Mistakes

Specman 18.09: Avoiding the Small Annoying Mistakes In almost every industry, one…

• 2 min read
enumerator , Specman , Functional Verification , e , e language , specman elite , xcelium

App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic Object…

Welcome back to the fourth installment of a special multi-part edition of the App…

• 2 min read
performance , SystemVerilog , Functional Verification , xcelium simulator

Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

Join us on September 14th for a free one-hour webinar on the finer aspects of the…

• less than a min read
uvm , Functional Verification , webinar , Duolos , uvm register layer

Adding a Patch Just in Time! — Or Can You Really Allow Yourself to Waste So Much…

One animation video - Patch Like The Wind - is worth a thousand words :) If you…

• 2 min read
Specman , Specman/e , Functional Verification , Specman e , tech tips , e language , team specman , save and restart

Evolution of DisplayPort

In 2006, the Video Electronics Standards Association (VESA) designed a new display…

• 2 min read
Verification IP , DisplayPort , verification

Tales From DAC: Netspeed and the Cadence Interconnect Workbench Pair Up

Services like facial detection, efficient cloud server workload management, artificial…

• 2 min read
cadence IWB , Interconnect Workbench , Functional Verification , gemini , netspeed

Is Ethernet Ready for the Automotive Market?

Consumer demand for advanced driver assistance and infotainment features are on the…

• 1 min read
Verification IP , VIP , Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet , TSN , Ethernet PHYs

Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server…

Learn about the challenges and solutions for integrating and verification PCIe(r…

• less than a min read
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