Featured

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Cadence in Collaboration with Arm Ensures the Software Just Works

The increase in compute and data-intensive applications and the need for lower power…

• 6 min read
SBSA , Emulation , Pre Silicon compliance Testing , Arm SystemReady

Automotive Revolution with Ethernet Base-T1

The automotive industry revolutionized the definition of a vehicle in terms of safety…

• 2 min read
Automotive , Verification IP , PTPOverMacSec , 100BaseT1 , uvm , Ethernet VIP , Functional Verification , Cadence VIP portfolio , VIP , Automotive Ethernet , 10BaseT1 , e , Ethernet , TSN , PTP , BaseT1 , 1000BaseT1 , Ethernet PHYs , MacSec , verification

Data Integrity for JEDEC DRAM Memories

With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b and…

• 3 min read
Verification IP , ddr5 , Memory , DDR5 DIMM , VIP , JEDEC , DRAM , lpddr5 , data integrity , NVDIMM , verification

5X “Time Warp” in Your Next Verification Cycle Using Xcelium Machine Learning

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated…

• 1 min read
xcelium ml , machine learning , xcelium , simulation

Quest for Bugs – The Constrained-Random Predicament

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of…

• 2 min read
compression , throughput , machine learning , Hard to Hit Bin , Coverage Closure , Regression , simulation

Modeling Configuration in PSS (Portable Stimulus)

Design patterns for modeling configuration and reconfiguration in PSS (Portable Stimulus…

• 4 min read
configuration , Perspec , portable stimulus , verification

Virtual Platforms to Shift-Left Software Development and System Verification

It is always beneficial to detect the defects early in the development phase prior…

• 5 min read
Virtual System Platform , virtual prototypes , helium

Leveraging Jasper UNR App for Code Coverage Signoff

Broadcom developed a code coverage signoff flow using Xcelium simulator’s constant…

• 5 min read
Jasper UNR app , System Design and Verification

Demystifying CXL.cache

If you have worked with Peripheral Component Interconnect Express (PCIe) in the past…

• 3 min read
CXL , Functional Verification , pcie 5 , VIP , PCIExpress , coherency , verification

Renesas Leverages Palladium + System VIP Solution for System Verification and Performance…

Verifying bus performance by analyzing bandwidth and latency over time in chips is…

• 5 min read

Enflame Accelerates the DFT and DFD Verification using Palladium

DFT (Design for Testability) provides the much-needed support to the manufacturers…

• 5 min read

How AMBA CHI Specification Has Evolved - CHI-E (r)evolutionary?

We covered CHI specification revisions A to D in my previous article , what about…

• 2 min read
Verification IP , Functional Verification , VIP , AMBA , CHI VIP

System Verification Scoreboard: Its Role and Partnership with Verification IPs

As discussed in the last installment of the blog, a robust system level scoreboard…

• 1 min read
Verification IP , scoreboard , SoC verification , Hardware Coherency

AMBA Distributed Translation Interface (DTI) for Arm System MMU

In ARM MMU-based systems, DTI protocol defines a standard way to communicate with…

• 1 min read
AMBA-DTI , AMBA VIP , AMBA Verification IP

Device Training for High Speed DRAMs

As the device frequencies and the data rates go up with every new generation of Interface…

• 3 min read
Verification IP , ddr5 , VIP , JEDEC , Training Modes , lpddr5 , lpddr5x , memory models , DDR5DIMM

LPDDR5 Verification from PHY to System Level

LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system…

• 6 min read

How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device?

DDR Memory is an important part of a wide array of electronic system designs in various…

• 2 min read
Verification IP , Industry Insights , Functional Verification , DFI 5.1 , VIP , SoC , DFI , storage , DFI Technical Group , memory models , DDR-PHY , DDR-PHY Interface

Who Inspires You? - An SVG Women's History Month Spotlight

This month, we join millions celebrating and recognizing the achievements of women…

• 6 min read

Addressing Hyperscalers' Requirements with Ethernet 800G

Cloud computing, IoT (Internet of Things), machine learning, big data, and data centers…

• 1 min read
Ethernet 800G , Verification IP , Ethernet VIP , Functional Verification , Hyperscalers , data centers , Ethernet 400G , cloud computing

Training Insights - Embracing Datapath Verification with Jasper C2RTL App

Current verification techniques cannot keep pace with the growing arithmetic nature…

• 2 min read
online , c2rtl , training , app , JasperGold , verification

MIPI UniPro 2.0 for Higher Data Rate Transmissions

MIPI specifications are widely used across the Mobile and IoT industries, mainly…

• 1 min read
UniPro , HS-LSS , VIP , MIPI

Mind reading? Almost. Specman New Typo Error Prediction Feature

Presenting Specman syntax error messages enhancement - provide suggestions to fix…

• 1 min read
Specman , e

Boost your CXL Verification From IP to System-Level

Knowingly or unknowingly, we are consuming huge volumes of data from getting up early…

• 6 min read
CXL , HIgh Speed Interconnect , PCIe , Compute Express Link

Employee Spotlight – Highlighting Our Colleagues in SVG!

Cadence’s SVG team would like to feature two team members who are making a difference…

• 5 min read

SoCs Verification Management, Traceability and Managing Risks in Semiconductor W…

With the increased complexity in SoC design and bigger teams, manually updating the…

• 4 min read
Verification planning and management , collaboration , vPlan , IBM , verification management , JIRA , Traceability , OpsHub , IBM DOORS NG , semiconductors , vManager

Optimizing CPU Time, TAT, and Disk Space using Cadence Xcelium Advanced Technologies…

Design for Testability (DFT) simulation is crucial to the SOC design process: rapid…

• 8 min read
System Design and Verification , PPA , Disk Space optimization , xcelium , HREF

Re-Timer – The Key for High-Speed Signal Transmission in USB4 Systems

The objective of USB4 protocol to achieve high speed signal transmission and thereby…

• 1 min read
Re-timer , USB4 VIP , VIP , usb4 , usb4 router

5G Network Revolution for Enhanced User Experience and Industry Digitalization

The emerging 5G network is the 5th generation of the cellular network. A 5G network…

• 1 min read
eCPRI , Verification IP , Enhanced Common Public Radio Interface , 5G Network , Ethernet VIP , Functional Verification , Ethernet standards , Synchronous Ethernet , Funcional Verification , sync
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