Featured

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Training Insights - Brand New Free Online Course on Perspec System Verifier for Beginner…

Cadence® Perspec System Verifier is a portable stimulus, system-on-chip (SoC) verification…

• 3 min read
Verification planning and management , verification strategy , Perspec , perspec system verifier , verification management , Verification Acceleration , System Verification , verification coverage , verification

Understanding Latency versus Throughput

One of the effects of adopting a High Level Synthesis design methodology is that…

• 2 min read
High-Level Synthesis , throughput , ESL High Level Synthesis , Team ESL , latency , ESL

Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and Py…

Join Cadence Training and Principal Application Engineer Daniel Bayer for this free…

• 1 min read
Verification planning and management , Verisium Debug , verification

How to Verify Complex PIPE Interface Based PHY Designs?

High-end SOC architectures today requiring more area and higher speed to transfer…

• 2 min read

How Renesas Reduced Automotive SoC Verification Time

The automotive world is conquering new technological heights, piggybacking on advanced…

• 5 min read
Automotive , verification time , Renesas , customer success , Verisium Manager , vManager

PCIe Lane Margining - What changed from Gen4 to Gen6?

With new PCIe 6.0 Base specifications rolled out, the move from NRZ (non-return-to…

• 3 min read
Verification IP | Functional Verification | VIP | System Verification | simulation | verification | , PCIe , pcie gen6 , PCI Express , PCI-SIG

CXL Enumeration: How Are Devices Discovered in System Fabric?

PCIe designed system fabrics rely on software enumeration by Operating System (OS…

• 2 min read

DisplayPort (DP) Tunneling over USB4

USB4 is an industry standard that tunnels three different protocol specifications…

• 2 min read
Verification IP , USB4 VIP , USB4v2 , USB4 DP Tunneling , DP Tunneling , usb4

Demystifying PCIe Lane Margining Technology

Lane Margining which was introduced in PCIe 4.0 and has been a very important technology…

• 3 min read
Verification IP | Functional Verification | VIP | System Verification | simulation | verification

USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling

USB4 Version 2.0 specification was recently released by the USB Promoter Group. This…

• 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2

Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Te…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol…

• 3 min read
CXL , Verification IP , cadence , Functional Verification , VIP , PCIe , coherency , TripleCheck

CXL 3.0 Scales the Future Data Center

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and Gen…

• 4 min read
CXL , Verification IP , Memory , System Design and Verification , VIP , PCIe , Funcional Verification , coherency , PCIe 6.0 , AI , data centers , cloud computing , verification

Unraveling New Introduced PCIe 6.0 L0p

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 4 min read
Verification IP , VIP , PCIe , pcie gen6 , verification

Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 4 min read
Verification IP , PCIe , pcie gen6 , verification

Unraveling PCIe 6.0 FLIT Mode Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 6 min read
Verification IP , featured , verification strategy , Functional Verification , VIP , PCIe , pcie gen6 , verification

Importance of MDIO Interface for Ethernet.

M edia I ndependent I nterface M anagement ( MIIM ), or M anagement D ata I nput…

• 1 min read
Verification IP , uvm , SoC verification , IP verification , Ethernet VIP , Functional Verification , Cadence VIP portfolio , MDIO Interface , Ethernet

USB4 Version 2.0 Announced

USB Promoter Group has announced the pending release of the USB4® Version 2.0 specification…

• less than a min read
usb4

Struggling with Coverage Convergence – Give your Verification Wings with Xcelium…

Functional verification consumes more than 70% of the labor invested in today’s SoC…

• 1 min read
coverage , machine learning , xcelium , simulation

USB4 Interoperability with Thunderbolt™︎ 3 (TBT3) Systems

One of the key goals for USB4 is to retain compatibility with the existing ecosystem…

• 2 min read
Verification IP , USB4 VIP , usb4 , usb4 router

Moving Beyond EDA: The Intelligent System Design Strategy

The rising customer expectations, intermingling fields and high performance needs…

• 5 min read
optimality , artificial intelligence , featured , intelligent system design

TSN-PTP: A Real-Time Network Clock Synchronizing Protocol

In a network containing multiple nodes, the need for synchronization between the…

• 2 min read
Verification IP , uvm , 5G Network , Ethernet VIP , Functional Verification , Cadence VIP portfolio , VIP , Automotive Ethernet , Ethernet , TSN , PTP , precision timing protocol , verification

Flash Toggle NAND 4.0 in a Nutshell

NAND Flash memory is now a widely accepted non-volatile memory in many application…

• 2 min read
Verification IP , Memory , flash , VIP , verification

Achieve 80% Less Late-Stage RTL Changes and Early RTL Bug Detection

It has become challenging to ensure that the designs are complete, correct, and adhere…

• 5 min read
featured , Jasper RTL Designer Signoff App , Jasper , Early Bug Detection

JEDEC UFS 4.0 for Highest Flash Performance

Speed increase requirements keep on flowing by in all the domains surrounding us…

• 2 min read
Verification IP , Memory , UniPro , MIPI Alliance , IoT , VIP , JEDEC , UFS , storage , MPHY

Coalesce Xcelium Apps to Maximize Performance by 10X and Catch More Bugs

Xcelium Simulator has been in the industry for years and is the leading high-performance…

• 1 min read
performance , featured , SoC , apps , xcelium , simulation , verification

Stay Ahead of Competition with Real-Time Cross-Team Collaborations

To stay ahead in competition in chip design real-time collaborations ensure traceability…

• 4 min read
collaboration , Palladium , verification management , Traceability , vManager

Xcelium PowerPlayBack App and Dynamic Power Analysis

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay…

• 5 min read
Dynamic Power Analysis , xcelium , power

Jasper C2RTL App for Datapath Verification

Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every…

• 5 min read
Datapath Verification , c2rtl , Jasper C2RTL , Equivalence Checking
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