Featured

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Covering Edges (part II)—“Inverse Normal” Distribution

In the previous example , we used the "select edge" to generate edge values for fields…

• less than a min read
AF , e language , Funcional Verification , functional coverage , coverage driven verification (CDV) , Aspect Oriented Programming

ADI Success Verifying SoC Reset Using X-Propagation Technology - Video

Analog Devices Inc. succeeded in both speeding up the simulation and debug productivity…

• 2 min read
x-prop , Low Power , debug , simvision , CPF , x-propagation , Incisive , UPF , MDV , GLS , verification , IES-XL

Recap of Another Successful Japan C-to-Silicon User Seminar

Back in November, our Japan office hosted a C-to-Silicon Compiler user meeting. They…

• 3 min read
C-to-Silcon , Renesas , Japan user group , high level synthesis , Fujitsu , Casio

New Capabilities in the C-to-Silicon Compiler 2013 Releases

2013 was a banner year for high-level synthesis and C-to-Silicon Compiler in particular…

• 4 min read
13.1 , C-to-Silcon , 13.2 , pipeline functions , high level synthesis , RTL schematic

Practical Guide to the UVM for $15 - Virginia, There is a Santa!

Wondering what to get the verification engineer on your list? You know, the one with…

• less than a min read
funtional verification , SystemVerilog , scoreboard , uvm , IEEE 1800 , Verification methodology , UVMWorld , OVM , Incisive Enterprise Simulator , Register Package , SoC , IEEE1800 , Register Layer , IES , IUS , VMM

Covering Edges (Part I) – Cool Automation

With random generation, most of the fields are due to be quite well covered. If…

• 2 min read
AF , e language , Funcional Verification , functional coverage , coverage driven verification (CDV) , Aspect Oriented Programming

Accelerating Code Coverage Using Palladium XP Rapid Adoption Kit

Code coverage is an effective tool in the verification process, giving insights into…

• 1 min read
IMC , System level verification and validation with Palladium XP , Rapid Adoption Kits , Palladium XP , UniCov Databases , Accelerated Code Coverage , RAKs , Accelerated Coverage , Assertions and Functional Coverage with covergroups.

High-Level Synthesis Now Spans the Datapath-Control Spectrum

When we talk to prospective high-level synthesis (HLS) customers, one of the slides…

• 1 min read
antenna interface controller , controll logic , ITRI , NAND flash controller , C-to-Silcon , Freescale , System C , rtl compiler , data access controller , datapath , high level synthesis , Fujitsu Semiconductor

High-Level Synthesis—What Expertise Is Needed for Micro-Architecture Tradeoffs?

My most recent blog post mentioned how utilizing new algorithms together with high…

• 5 min read
RAM , micro-architecture , hardware , C-to-Silcon , C , SystemC , HLS , C++

Accelerated Code and Functional Coverage Using Palladium XP

Code coverage is an effective tool in the verification process—giving insights into…

• 2 min read
IMC , Cadence Online Support , UXE , Palladium XP , Incisive Verification Environment , support.cadence.com , Accelerated SV Covergrooups , Accelerated Coverage , IES

Coverage Unreachability UNR App - Rapid Adoption Kit

The Cadence Incisive Enterprise Verifier (IEV) team recently developed a self-help…

• 3 min read
coverage , Unreachability , RAK , UNR , IEV , Incisive Enterprise Simulator (IES) , Formal verification

Generic Dynamic Run-Time Operations with e Reflection, Part 1

Untyped Values and Value Holders The reflection API in e not only allows you to perform…

• 3 min read
AF , Functiional Verification , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming , reflection

Starting Virtual Platform Simulation with Cadence Software Developer

Last time, I provided an introduction to the Eclipse setup for the Cadence Virtual…

• 4 min read
eclipse , Virtual System Platform , Embedded Software Debugging , Incisive

Combining the Linux Device Tree and Kernel Image for ARM

Back in 2010, I wrote two articles about a SystemC model used to load the Linux kernel…

• 2 min read
Virtual System Platform , virtual platforms , TLM , ARM kernel image , virtual prototypes , VSP , zimage , boot loader , System Design & Verification , SystemC , Linux device tree , ARM , system-level , linux , Jason Andrews , ESL , kernel

Getting Started with the Cadence Virtual System Platform: Software Developer

Cadence Software Developer is an exciting Eclipse-based product for developing, debugging…

• 4 min read
eclipse , Virtual System Platform

Trends in Using Software for System Verification

There is a clear trend to use more software running on the CPUs of a design for system…

• 2 min read
Palladium XP , hybrid engines , linux kernel , Virtual Platforms

e Macro Debugging

When creating a testbench using the MDV methodology, you want to write intelligent…

• 4 min read
AF , Functional Verification , Debug Performance , e macro debugging , e macros , macro debugging , e language , coverage driven verification (CDV) , macros

Slow Winter or New Spring for Hardware Design?

If you're looking for an entertaining gonzo take on the history and current state…

• 4 min read
5G , algorithms , microsoft , H.265 , James Mickens , process scaling , Hardware design , HEVC , 4K , Apple M7 , Moto X , high level synthesis , Adreno 320 , System Design and Verification

HDMI 2.0 – Ushering in the Next Generation of Ultra HD TV

The future of television is being defined by two key technologies: organic light…

• 2 min read
Verification IP , HDMI 2.0 , Ultra HD , 4K TV , cadence , VIP , HDTV , SoCs

Configurable Specman Messaging Webinar Archive Available Now

Configurable Specman Messaging for Improved Productivity Webinar Archive Available…

• 1 min read
IEEE 1647 , Specman/e , AVS , Functional Verification , Specman e , Testbench simulation , Incisive Enterprise Simulator , e-language , configurable messaging , EDA , e , webinar , e language , Specman messaging , Specman C

Getting Ready for ESL with Emulation!

Next week on Monday, August 19th, Gary Smith will run a webinar called " ESL - Are…

• 2 min read
Low Power , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Acceleration , System to Silicon Verification , Dynamic Power Analysis , System Design and Verification , System Development Suite , embedded software , Gary Smith , GSEDA , Palladium XP , Emulation , Atrenta , Schirrmeister , ESL , low power optimization

New Specman Coverage Engine (Part III)—Use of Extension Under "when" vs. Using Instance…

In both previous coverage blog posts ( Part I and the Part II ), we showed two solutions…

• 2 min read
AF , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming

New Specman Coverage Engine (Part II) - Using Instance-based Coverage Options for…

In the last coverage blog , we showed how the extensions of covergroups under when…

• 3 min read
AF , coverage parameterization , Specman , coverage , covergroups , instance-based coverage , subtypes , e language , extensions under subtypes , Funcional Verification , Incisive Enterprise Simulator (IES)

Fujitsu Gets 3x Faster Regression with Incisive Simulator and Enterprise Manager

Verification regression consumes expensive compute resources and precious project…

• 2 min read
performance , IEM , Enterprise Manager , simulation , Regression Farm , IES-XL

Verification IP: Five More Things I Learned By Browsing Cadence Online Support

After talking about some tips for using trace files in debugging Verification IP…

• 4 min read
Verification IP , NVMe , NVMe PureView VIP Usage , Instantiating VIP models with SystemVerilog , USB , Denali Migration Guide , Integrating USB 3.0 PHY DUT , PHY DUT , Verification Flow USB , PureView USB 3.0 VIP.

Cadence Verification IP AppNotes Demonstrate the Use of Trace Files in Debugging

Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility…

• 4 min read
LFPS , Verification IP , Trace files , Denali to Cadence Migration , debug , PureSpec , VIP , PCIE2.0 , Application Notes , Appnotes , USB3.0 , Low Frequency Periodic Signaling , SuperSpeed USB Inter-Chip , debugging , SSIC

How-To AppNotes on Cadence Palladium-XP Help Users Get the Basics Right

In simulation acceleration, there are multiple reasons for using gate-level netlists…

• 3 min read
Acceleration , netlist files , Palladium , LSF , Palladium XP , Emulation , Simulation acceleration , Cadence Application Notes , Compute server , Load Sharing Facility

The Art of Modeling in e

Verification is the art of modeling complex relationships and behaviors. Effective…

• 4 min read
AF , Specman , Incisive , e language , Funcional Verification , coverage driven verification (CDV) , Modeling
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