Featured

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package

The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture…

• 5 min read
AF , uvm , Specman , debug , Functional Verification , Incisive , UVM ML , e language , simulation

Generic dynamic run-time operations with e reflection Part II

Field access and method invocations In the previous blog , we explained what are…

• 4 min read
AF , Functiional Verification , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming , reflection

Looking Back at a Great Week for System Design!

Reflecting on last week at ARM TechCon, together with our close partner ARM, we had…

• 3 min read
debug , System Design and Verification , embedded software , hybrid , ARM TechCon 2014 , ARM , verification

Cadence Palladium Platform and ARM Fast Models - Making the Future the Present

In its 10th year now, ARM TechCon is in full swing this week at the Santa Clara Convention…

• 3 min read
NVIDIA , Palladium , hybrid , Emulation , ARM Fast Models , ARM

Troubleshooting Incisive Errors/Warnings with nchelp/ncbrowse and Cadence Support…

I joined Cadence in July 2000 and was immediately put on a three-month training to…

• 4 min read
nchelp , Incisive , error , xcelium simulator , troubleshooting , mnemonic , xcelium , utilities , xmhelp

The webinar on “Effective system-level coverage” does an effective coverage of the…

If you're anything like I am, you listen to webinars with one ear, occasionally checking…

• 4 min read
system-level coverage , PXP , hardware assisted verification , webinar , Palladium XP , hardware acceleration , EDA webinar , hardware accelerated verification

Objection Mechanism Synchronization Between SystemVerilog and e Active Verification…

Suppose you have two verification components, each driving its own portion of the…

• 4 min read
AF , UVM-ML , e-SV , debug , objection mechanism , Functional Verification' signal integrity , Incisive Enterprise Simulator (IES)

Challenges and Applications in a 3D World

As the 3-D memory market matures, it continues to incubate new application opportunities…

• 1 min read
Verification IP , Memory , 2.5D Memory , 3D memory , VIP , Memory Model Portfolio , HMC , HBM , memory IP , Wide IO2 , MMAV

Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More

The profiler helps to figure out the components or the code streams that take the…

• 2 min read
SystemVerilog , uvm , profiling , Incisive , post-simulation profiling , verification

Boost Efficiency and Performance of Simulation Acceleration Through New Rapid Adoption…

The state-of-the-art Palladium XP hardware/software verification computing platform…

• 2 min read
ICE , sim accel , IXCOM , Palladium XP , COS Cadence Online Support , Simulation acceleration , hsv , RAKs , stb

Verification IP: 7 Things I Learned By Browsing Cadence Online Support Last Mont…

Using proven Cadence Verification IP (VIP), you can verify SoC designs faster, more…

• 4 min read
Verification IP , IVD , Cadence app notes , MDIO Interface , VIP , Cadence Online Support , DpDm , SOMA to UVM Configuration

New VIP RAKs Help in Learning Integration of Ethernet GMII and M-PCIe into SystemVerilog…

There is always a demand for learning something simply and quickly on your own in…

• 3 min read
SystemVerilog , Verification IP , uvm , GMII , Rapid Adoption Kit , VIP , M-PCIe , RAK

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing…

Cadence Online Support, https://support.cadence.com/ , provides access to support…

• 5 min read
COS , IMC , SystemVerilog , random stability , LPS , UVM-ML , CPF , debugging tips , Cadence Online Support , UVM ML , troubleshooting , irun , IES , vManager

Implementing User-Defined Register Access Policies with vr_ad and IPXACT

The register and memory package vr_ad for Specman is used in pretty much every verification…

• 2 min read
AF , Specman , debug , vr_ad , e code , Funcional Verification , Incisive Enterprise Simulator (IES) , ipxact

PCIe Gen4 LIVE Demo at PCI-SIG DevCon Next Week

The PCI-SIG has (FINALLY) released the PCIe 4.0 rev 0.3 specification for members…

• 1 min read
Verification IP , IP , PCI Express 3.0 , Gen3 , NVMe , VIP , M-PCIe , MPCIe , PCIe , PCIe Gen3 , PCI-SIG

DAC 2014—ESL Design Is Dead... Long Live ESL!

Next week the EDA industry is getting together in San Francisco for Design Automation…

• 20 min read
DAC , Frank Schirrmeister , ESL

sync and wait Actions vs. Temporal Struct and Unit Members

Using sync on a temporal expression (TE), does not guarantee that the execution will…

• 2 min read
AF , events , IntelliGen , Specman , units , e code , temporal expressions , Funcional Verification

e and SystemVerilog: The Ultimate Race

For years we've watched the e and SystemVerilog race via countless presentations…

• 1 min read
IEEE 1647 , SystemVerilog , IEEE 1800 , simulation performance , e , Adam Sherer , UVM ML , Funcional Verification , IES

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing…

In my first blog of this quarterly series, I focused on how Rapid Adoption Kits …

• 6 min read
IMC , low power simulation , uvm , Specman , LPS , x-propagation , RAK , incisive simulation , LSF , Glitches , state retention , drm , SystemC , vMananger , IES-XL

Applying Software-Driven Development Techniques to Testbench Development

Over the past couple of years there has been some interest in applying a software…

• 1 min read
AF , Specman , debug , e code , Funcional Verification , unit testing , Incisive Enterprise Simulator (IES)

Cadence Announces Verification IP for MIPI SoundWire and C-PHY

Anyone who has been involved in designing mobile devices in recent years is familiar…

• less than a min read
Verification IP , MIPI Alliance , cadence , audio , PureSpec , Slimbus , VIP , MIPI , CSI , M-PCIe , Denali , C-PHY , Soundwire , M-PHY

The Importance of Ecosystems in the Internet of Things Era

As we develop electronics in early 2014, the battle between processor architectures…

• 4 min read
ARM ecosystem , System Design and Verification , electronics design , Internet of Things , ARM , embedded systems

Randomizing Error Locations in a 2D Array

A design team at a customer of mine started out with Specman for the first time…

• 3 min read
AF , IntelliGen , Specman , e code , stimuli , Generation , Funcional Verification

New Incisive Verification App and Papers at DVCon by Marvell and TI

If you're an avid reader of Cadence press releases (and what self-respecting verification…

• 1 min read
Formal Analysis , formal , Funcional Verification , DVCon 2014 , Formal verification , Assertion-based verification

Incisive vManager at DVCon - Come See It!

Have you heard the news? There is a new version of vManager announced this week,…

• 1 min read
collaboration , : Functional Verification , Verification methodology , cadence , Functional Verification , vPlan , Verisity , DVcon , metric-driven verification , functional coverage , vManager

e Language Editing with Emacs

Specman and e have been around for a while, and some clever people have developed…

• 1 min read
AF , Specman , Incisive Debug Analyzer , e code , xemacs , Funcional Verification , editing , emacs

Incisive Verification: Top 10 Things I Learned While Browsing Cadence Online Support…

There is always a demand, in most corners of the world today, for learning and troubleshooting…

• 9 min read
IEEE-1801 , LPS , App Note Incisive Simulation , Cadence Online Support , RAK , UVC , UPF , IES

Cadence and AMD Add New UVM Multi-Language Features

The UVM Multi-Language Open Architecture open-source library was recently updated…

• 2 min read
IEEE 1647 , SystemVerilog , uvm , IEEE 1800 , UVM-ML , VCs , Incisive , e , IEEE 1666 , Accellera , SystemC , Questa , IES-XL
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