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Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus
Verification
Latest blogs

TLM 2.0 As Part Of The EDA360 Vision

Ann Steffora Mutschler recently covered in her blog the progress the industry has…

• 1 min read
TLM , virtual platform , TLM 2.0 , EDA360 , virtual prototype , SystemC , Synthesis , System Design and Verification

EDA360 Is More Than Design IP Plus Software Drivers

I checked my Linked-In messages the other day and saw a survey by Girish Patil with…

• 2 min read
IP , Functional Verification , Virtual Chips , Phoenix , inSilicon , VIP , EDA360 , Sand

The Future of OVM, VMM, and UVM

In my last blog , I took a look back at the history of how we got to the first delivery…

• 3 min read
SystemVerilog , uvm , methodology , Functional Verification , Open Verification Methodology , OVM , VIP , Accellera , Accellera VIP TSC , VMM

Tech TIP: Incisive Formal GUI Updates - Making It Easier

The Incisive Formal GUI has had some recent changes made to it. You asked for the…

• less than a min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

UVM World Community Site Now Available!

Yesterday morning, the verification world was buzzing with the first release of the…

• 1 min read
uvm , Verification methodology , Functional Verification , OVM , VIP , Accellera VIP TSC

UVM - 10 Years in the Making ...

In case you the missed the news today, the Accellera VIP TSC released the first version…

• 3 min read
SystemVerilog , uvm , Specman , OVM ML , Functional Verification , OVM , OVM e , Coverage-Driven Verification , CDV , vr_ad , OVM SV , e , OVM-e , Accellera , coverage driven verification (CDV) , eRM , Accellera VIP TSC , OVMWorld

Initial Release of the UVM Now Available!

As Richard Goering just reported , the Accellera VIP Technical Subcommittee (TSC…

• 2 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

EDA360: Cool People Creating Cool Stuff

Now that we have had some time to reflect on the meaning of EDA360 , it occurred…

• 4 min read
EDA360 , Systemm Design and Verification , OpenStreetMap , Embedded Linux , Embedded Software Engineer

Inside Cadence: Training for EDA360

Over the past few weeks all of Cadence's Verification and Systems Solutions Applications…

• 5 min read
Specman , TLM , OVM ML , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , OVM , VIP , OVM e , CtoSilocon , OVM SV , e , Enterprise Manager , Palladium XP , MDV , IEV , Incisive Enterprise Simulator (IES) , IFV , IES-XL

FMCAD Call for Papers Extended to May 12

Team Verify would like to inform you about the final call for papers for FMCAD 2010…

• 7 min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

Informative Tweets on WHEN Inheritance

Earlier today a lively and very instructive thread on the relative virtues of WHEN…

• 3 min read
SystemVerilog , when sub-typing , tweeting , Specman , Functional Verification , when inheritance , OVM , OVM e , OVM SV , e , Twitter , AOP , IES-XL

What Does EDA360 Mean for Verification Engineers?

I trust that most of you have seen the recent flurry of blog posts and articles about…

• 2 min read
uvm , IP , Verification methodology , OVM , VIP , EDA360

System Realization activities at CDNLive! EMEA this week

CDNLive! EMEA will be held in Munich again this year, and there’s lots of news about…

• 2 min read
System Design and Verification , cdnLive! system realization

See You at CDNLive! EMEA

Today, Team Specman reported that next week's CDNLive! is shaping up to be a big…

• 2 min read
CDNLive!ive! , System Design and Verification

2010 CDNLive Munich Guide for Specmaniacs

Good news for Specmaniacs based in the EU: next week from May 4-6 is the annual CDNLive…

• 2 min read
Specman , CDNLive , Functional Verification , Cadence VIP portfolio , OVM , OVM e , e , Mike Stellfox , techtorial

Team Verify's 2010 CDNLive Munich Guide

We're excited to report that next week's annual CDNLive! event in Munich will feature…

• 1 min read
ABV , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Contributions , SVA , PSL , MDV , IEV , IFV

Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%

More and more often it takes a village to achieve verification success. As reported…

• 1 min read
Functional Verification , Incisive , xilinx , IES , FPGA , Matlab , IES-XL

Verified by e/Specman: The Palladium XP Verification Computing Platform

After much anticipation, it feels great to be free to proclaim that e /Specman (as…

• less than a min read
metric driven verification (MDV) , Functional Verification , e , Palladium XP , MDV , IES-XL

Ubuntu on ARM is Growing

Based on the title, you probably guessed I'm talking about growing in popularity…

• 6 min read
virtual platform , System Design & Verification , Embedded Linux , QEMU

UVM Based on OVM 2.1.1: What a Great Idea!

Regular readers know that I have been urging the Accellera VIP TSC to base its Universal…

• 2 min read
uvm , Verification methodology , OVM , Functional Verification' signal integrity , Contributions , Accellera

When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog…

Building on the packet generation example of part 1 , and the coverage examples of…

• 3 min read
IEEE 1647 , SystemVerilog , Specman , Object Oriented Programming , Functional Verification , e , OOP , Aspect Oriented Programming , AOP , IES-XL

Specman-SimVision webinar on April 22 (next week!)

We interrupt Corey's excellent "When Less Is More" series to announce a Specman-SimVision…

• 1 min read
IEEE 1647 , debug , Functional Verification , simvision , e , multi-language , IES-XL

Hate Writing Assertions? No problem: let Automatic Formal Analysis do the work

OR: “Leverage automatic checks extracted from designs without writing a single assertion…

• 4 min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

New Blog: All About Integrated formal, Simulation, and Assertion-Based Verification…

End-users of Incisive Formal Verifier ("IFV"), Incisive Enterprise Verifier ("IEV…

• 1 min read
ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , OVM , Incisive , Twitter , MDV , IEV , IFV

When Less Is More, Part 2: Is e Code Really Up to 3x More Compact Than SystemVerilog…

In my last post I wrote some packet generation code to validate the claim that e…

• 4 min read
IEEE 1647 , SystemVerilog , Functional Verification , OVM , OVM e , CDV , OVM SV , e , coverage driven verification (CDV) , Aspect Oriented Programming , AOP , IES-XL

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines…

• 3 min read
IEEE 1647 , SystemVerilog , Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , e , OOP , ClubT , Aspect Oriented Programming , AOP , IES-XL

Accessing Physical Memory and Registers in a Virtual World

When working with Virtual Platforms that are running operating systems it's sometimes…

• 3 min read
Registers , Memory , virtual platforms , Virtual , System Design and Verification

Tweeting From a Standards Meeting: Good or Bad?

In my last blog entry , I mentioned that I was able to keep up with a lot of the…

• 2 min read
uvm , tweeting , meetings , Functional Verification , texting , Accellera , EMAIL
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