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Sanjiv Bhatia
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17.4
IC Packaging & SiP design
IC Packagers
Allegro Package Designer
17.4-2019
PCB design
Allegro

The Year That Was: Cadence IC Packaging and SiP Blogs in 2021

23 Dec 2021 • 4 minute read

 With only a few days left in 2021, you must be wrapping things up at work. This year was challenging like no other as COVID-19 struck many of us again. However, even with restrictions and daily virus updates spilling over from 2020, we adapted better and carried on.

2021 continued to be a good year for us in the blogging department too. We published 16 blog posts in the IC Packagers series, averaging more than one per month. But more than the number of posts published, the overwhelming response we received from all of you, our readers, is what gives us the biggest pleasure. Knowing that you found our posts useful because they informed you about useful features or solved immediate problems encourages us to bring you more such posts in the coming year.

So, here we are, saying a big thank you, and presenting a list of some of the most popular posts of 2021!


  • IC Packagers: An Introduction to Off-Grid Degassing
    By Tyler | 2 Feb 2021
    The off-grid degassing tool helps find problem areas even if all the hole patterns recommended by the OSAT or foundry are added. Read this post to learn how this tool can save you hours of time by automating what would otherwise be a heavily manual process.

  • IC Packagers: A New Way to Create Structures
    By Tyler | 9 Feb 2021
    Here’s Tyler bringing a new twist to established routing technology. Structures, which were formerly called via structures, are very flexible, and find application across many flows. Read this post for information on these handy, reusable blocks of routing and quickly fan out the most complex of component interfaces.

  • IC Packagers: Analyze, Simulate, and Resolve Signal Integrity Issues Using In-Design Analysis Flows
    By avijeet | 1 May 2021
    Shrinking IC Package design cycles means that routing issues must be addressed as early as possible. How do you achieve that without learning complex simulation tools? Read this post where Avijeet explains a quick and accurate way using In-Design Impedance and Coupling workflow powered by the SigrityTm solver from within Allegro Package Designer Plus.

  • IC Packagers: How to Quickly Push Design Connectivity across a Design
    By avijeet | 23 Mar 2021
    Updating the netlist of a co-design die or BGA in the middle of the design cycle is no doubt a big challenge. More so if you use time-consuming, error-prone, and difficult-to-review traditional methods of updating connectivity. Read this post to know about a neat solution using push connectivity.

  • IC Packagers: 17.4-2019 Hotfix 019 Is Here! What Does That Mean?
    By Tyler | 11 Aug 2021
    Tyler talks about some changes that came with HotFix 019 of Release 17.4-2019. Although there are many enhancements and new features, this post lists four major features you should use: layer-based degassing, acute angle cover improvements, the new GDSII Verification tool, and Layer Compare.

  • IC Packagers: Analyzing and Fixing Wire Bond-Specific Design Issues
    By avijeet | 26 May 2021
    Wire bonds are almost ubiquitous in packaging. Any improvement, whether in productivity or quality, of wire bonds affects the overall design. Read this blog post to explore the wire bond-specific design integrity checks that find and, wherever possible, automatically resolve wire bonding-specific package design issues.

  • time-consuming
    IC Packagers: Understanding Stadium-Style Cavity Package Design
    By avijeet | 30 Jun 2021
    Design complexity and space constraints are pushing designers towards innovative novel solutions. Placing a die inside a cavity is the most common and effective technique and you have probably used it if you are designing an application for the automotive or telecom domain. Read this post for the steps to wire bond a design for an open stadium cavity style.

  • IC Packagers: Reuse Wirebond Placement with Place Replicate Modules
    By avijeet | 29 Jul 2021
    Allegro® Package Designer Plus provides Place replicate commands to replicate and reuse modules in the same or other designs. The good news is that the Place replicate commands are now enabled for packaging designs. Read this post to know how to reuse wire bonds in designs using the Place replicate commands.

Wish you a very happy new year! And, with a promise to bring you more value with our posts next year we sign off for 2021. Keep reading and sharing to encourage us. See you in 2022!


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