• Discussion

  Type casting boolean? Locked

  16736 views
  2 replies
  Latest over 16 years ago
  by markbeck
• Discussion

  CadenceRC area report Locked

  19211 views
  6 replies
  Latest over 16 years ago
  by Hava
• Discussion

  SKILL arithmetic comparisons Locked

  16805 views
  3 replies
  Latest over 16 years ago
  by sri125
• Discussion

  how do I copy a DEHDL design? Locked

  15669 views
  8 replies
  Latest over 16 years ago
  by Jerry GenPart
• Discussion

  ASSURA 3.1.6 - errors on input/output pins Locked

  1426 views
  2 replies
  Latest over 16 years ago
  by yoyega
• Discussion

  SKILL language basics and SKILL script for converting and resizing CMOS transistors Locked

  14223 views
  2 replies
  Latest over 16 years ago
  by archive
• Discussion

  0.5mm pitch BGA fan out Locked

  20710 views
  12 replies
  Latest over 16 years ago
  by girish
• Discussion

  library to cdl or gdsII Locked

  13418 views
  0 replies
  Started over 16 years ago
  by kashvi
• Discussion

  Capture Quirks Locked

  12972 views
  2 replies
  Latest over 16 years ago
  by EvanShultz
• Discussion

  Synthesizing Mixed Verilog-VHDL in RTL Compiler? Locked

  16054 views
  2 replies
  Latest over 16 years ago
  by Scrivner
• Discussion

  Nanoroute writes out def without the property definition section..... Locked

  15339 views
  6 replies
  Latest over 16 years ago
  by NAADHAN
• Discussion

  How to get cursor coordinate? Locked

  17642 views
  2 replies
  Latest over 16 years ago
  by Andrew Beckett
• Discussion

  Hard macros power routing issues Locked

  23994 views
  19 replies
  Latest over 16 years ago
  by verysmart
• Discussion

  Beginners guide to skill scripting Locked

  18025 views
  2 replies
  Latest over 16 years ago
  by xizzling
• Discussion

  non-hierarchy EDIF or FATF Locked

  1287 views
  1 reply
  Latest over 16 years ago
  by luvishis