• Discussion

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  13990 views
  2 replies
  Latest over 16 years ago
  by frankz
• Discussion

  clock tree quality Locked

  18709 views
  10 replies
  Latest over 16 years ago
  by frankz
• Discussion

  Why do we go for virtual clocks?? Locked

  18523 views
  7 replies
  Latest over 16 years ago
  by frankz
• Discussion

  ncvlog: *E,RIMPCD: error reading implicit cds.lib Locked

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  4 replies
  Latest over 16 years ago
  by AshVarma
• Discussion

  Metal layer constraining Locked

  13955 views
  2 replies
  Latest over 16 years ago
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• Discussion

  Cadence IC 6.1.3 Simualtion Locked

  7790 views
  9 replies
  Latest over 16 years ago
  by StreamCX
• Discussion

  Internal Error on IUS8.2-b003 Locked

  13774 views
  1 reply
  Latest over 16 years ago
  by StephenH
• Discussion

  can lay out engineer change the width of a resistor? Locked

  15017 views
  4 replies
  Latest over 16 years ago
  by Andrew Beckett
• Discussion

  Replay of Script

  14154 views
  2 replies
  Latest over 16 years ago
  by Jmac0585
• Discussion

  Auto-Router Clearence Conflicts Locked

  12848 views
  0 replies
  Started over 16 years ago
  by PherricOxide
• Discussion

  Setting "schematic" as stop view in Spectre netlister Locked

  3290 views
  2 replies
  Latest over 16 years ago
  by hkutuk
• Discussion

  Importing a Mentor Neutral File into Allegro??? Locked

  17828 views
  7 replies
  Latest over 16 years ago
  by AcAe
• Discussion

  SKILL equivalent for MOD function

  18198 views
  1 reply
  Latest over 16 years ago
  by Nagaraj Shanmu
• Discussion

  Setting of Constraint region... Locked

  16564 views
  6 replies
  Latest over 16 years ago
  by Ejlersen
• Discussion

  How to export from protel PCB to Allegro PCB? Locked

  13960 views
  2 replies
  Latest over 16 years ago
  by ELEKVN