• Discussion

  doing coverage for 64 bit field in specman Locked

  14173 views
  1 reply
  Latest over 16 years ago
  by StephenH
• Discussion

  IUS 8.2 internal error Locked

  14730 views
  3 replies
  Latest over 16 years ago
  by StephenH
• Discussion

  Behavior of multiple label-pins while extraction Locked

  14965 views
  2 replies
  Latest over 16 years ago
  by flang
• Discussion

  via change & constraint error Locked

  671 views
  1 reply
  Latest over 16 years ago
  by pakistan
• Discussion

  importing FPGA design into Design Entry HDL Locked

  13372 views
  1 reply
  Latest over 16 years ago
  by redwire
• Discussion

  problem opening allegro 15.5.1 files in 16.0 Locked

  13258 views
  1 reply
  Latest over 16 years ago
  by redwire
• Discussion

  back annotate from allegro(pcb) to orcad(schematic) Locked

  7954 views
  5 replies
  Latest over 16 years ago
  by pakistan
• Discussion

  Change the threshold voltage ?? Locked

  16974 views
  3 replies
  Latest over 16 years ago
  by sience2peace
• Discussion

  Simvision Freq calc button not available Locked

  15588 views
  0 replies
  Started over 16 years ago
  by Chintanm
• Discussion

  How do I create custom strokes in Allegro Locked

  16982 views
  6 replies
  Latest over 16 years ago
  by blockst
• Discussion

  Errors while running DRC Locked

  15015 views
  3 replies
  Latest over 16 years ago
  by Austin CAD Guy
• Discussion

  ncelab: *F,INTERR: INTERNAL ERROR while running ncsc_run on a systemC & verilog design Locked

  2063 views
  3 replies
  Latest over 16 years ago
  by Mickey
• Discussion

  route command at PCB router Locked

  13340 views
  1 reply
  Latest over 16 years ago
  by oldmouldy
• Discussion

  Some issues with System Architect Locked

  12949 views
  0 replies
  Started over 16 years ago
  by Javinder
• Discussion

  FYI - New Book available (Happy Holden, HDI techniques), FREE Locked

  2476 views
  2 replies
  Latest over 16 years ago
  by girish