• Discussion

  Elaborating the design hierarchy Locked

  14730 views
  1 reply
  Latest over 16 years ago
  by TIRTH
• Discussion

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  1 reply
  Latest over 16 years ago
  by TIRTH
• Discussion

  annotating switching activity Locked

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  7 replies
  Latest over 16 years ago
  by alexsieh
• Discussion

  About Noise-Aware PLL Flow Locked

  14464 views
  1 reply
  Latest over 16 years ago
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• Discussion

  4 Layer PCB for 400 MHz Frequency Locked

  13303 views
  1 reply
  Latest over 16 years ago
  by CubbyBear
• Discussion

  cross talk effect Locked

  13634 views
  0 replies
  Started over 16 years ago
  by surajece01
• Discussion

  cross talk effect Locked

  13650 views
  0 replies
  Started over 16 years ago
  by surajece01
• Discussion

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  4 replies
  Latest over 16 years ago
  by girish
• Discussion

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  19820 views
  6 replies
  Latest over 16 years ago
  by JMGGL
• Discussion

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  38439 views
  2 replies
  Latest over 16 years ago
  by Randy R
• Discussion

  Skill code for accessing properties of a pin shape in Layout view Locked

  15337 views
  2 replies
  Latest over 16 years ago
  by mandeep
• Discussion

  Accuracy problem Locked

  15103 views
  2 replies
  Latest over 16 years ago
  by pakistan
• Discussion

  Systemverilog-2008 and variadic `define macros? Locked

  14981 views
  1 reply
  Latest over 16 years ago
  by Shalom B
• Discussion

  Conversion of an Integer port in VHDL to equivalent in Verilog Locked

  16676 views
  2 replies
  Latest over 16 years ago
  by cubicle82
• Discussion

  Problem moving symbol - get "Symbol has no pin 1" error Locked

  1676 views
  3 replies
  Latest over 16 years ago
  by mgcorr