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  • Not Answered

    in Allegro design entry HDL, "add a component" : footprint does not exist for that part 0

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    Latest over 2 years ago
    by rg13
  • Discussion

    Is there a way to change the cordinate of highlight object? Locked

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    4 replies
    Latest over 2 years ago
    by Andrew Beckett
  • Discussion

    generate a netlist of schematic designed in spectre. Locked

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    5 replies
    Latest over 2 years ago
    by Andrew Beckett
  • Discussion

    SystemVerilog count the $error() output during simulation Locked

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    1 reply
    Latest over 2 years ago
    by StephenH
  • Discussion

    Glitch Locked

    7864 views
    3 replies
    Latest over 2 years ago
    by VIRAJ PANCHAL
  • Discussion

    ADE Assembler: automatic ADC gain error extraction Locked

    11758 views
    11 replies
    Latest over 2 years ago
    by Andrew Beckett
  • Discussion

    LVS mismatch when transistor body is not detached/integrated Locked

    1965 views
    1 reply
    Latest over 2 years ago
    by supriyo1985
  • Answered

    Panelization Syncronization Issue +1

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    2 replies
    Latest over 2 years ago
    by BaldEngineer
  • Discussion

    How to sample a signal at specific (non-uniform) points in time? Locked

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    7 replies
    Latest over 2 years ago
    by DomiHammerfall
  • Suggested Answer

    How to Download the Discrete Cadence PSpice Model Library for Bipolar Transistors 0

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    14 replies
    Latest over 2 years ago
    by digital1
  • Answered

    Presentation Slides +1

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    2 replies
    Latest over 2 years ago
    by Colinda
  • Answered

    Lectures availability +1

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    2 replies
    Latest over 2 years ago
    by Colinda
  • Not Answered

    Capture CIS 2023 opens normally once and then closes; opening it again may fail. 0

    5378 views
    3 replies
    Latest over 2 years ago
    by rg13
  • Discussion

    In-Design Impedance Analysis

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    1 reply
    Latest over 2 years ago
    by geda
  • Discussion

    How to plot INL & DNL of converter...? Locked

    3922 views
    2 replies
    Latest over 2 years ago
    by VIRAJ PANCHAL
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