• Discussion

  is it possible to pass integer to verilog-a module? Locked

  11821 views
  2 replies
  Latest over 4 years ago
  by delgsy
• Discussion

  Edge Triggered Current Source Locked

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  4 replies
  Latest over 4 years ago
  by Kevin Buck
• Discussion

  How to confirm connections which are connected by "net name" in visible way Locked

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  1 reply
  Latest over 4 years ago
  by Andrew Beckett
• Discussion

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  1954 views
  1 reply
  Latest over 4 years ago
  by Andrew Beckett
• Discussion

  Orcad PCB (allegro) not using GPU over USB Locked

  11566 views
  1 reply
  Latest over 4 years ago
  by RFinley
• Discussion

  Allegro part of DPI does not support scaling above 150% Locked

  10006 views
  0 replies
  Started over 4 years ago
  by JON123
• Discussion

  datasheets for difference of Allegro PCB and OrCAD Professional Locked

  11717 views
  2 replies
  Latest over 4 years ago
  by JON123
• Discussion

  speeding up .hb at a certain stage Locked

  12320 views
  6 replies
  Latest over 4 years ago
  by FormerMember
• Discussion

  Pin size on CMOS circuit layout design Locked

  9612 views
  0 replies
  Started over 4 years ago
  by Senan
• Discussion

  Export Plot to CSV using SKILL Locked

  20612 views
  7 replies
  Latest over 4 years ago
  by rod1
• Discussion

  Can I align pin numbers in edit part windows in Orcad Capture? Locked

  12164 views
  1 reply
  Latest over 4 years ago
  by steve
• Discussion

  IC 6.1.7 on RHEL8 Locked

  13918 views
  2 replies
  Latest over 4 years ago
  by ddelrio
• Discussion

  About Multi technology simulation Locked

  10571 views
  2 replies
  Latest over 4 years ago
  by ichiro
• Discussion

  How to embed waveform setup (.grf) in maestro views? (or: how to propagate .grf files along with their associated cells?) Locked

  10311 views
  2 replies
  Latest over 4 years ago
  by dontpanic
• Discussion

  How to report running time of simulation in adexl? Locked

  9511 views
  1 reply
  Latest over 4 years ago
  by Holz