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Forum - Thread List
  • Discussion

    Path mapping for C Firmware source files when debugging Locked

    27557 views
    6 replies
    Latest over 4 years ago
    by rvphilip
  • Discussion

    "Shape Void Rectangle" Allegro 17.4

    2548 views
    4 replies
    Latest over 4 years ago
    by rgmeier3
  • Discussion

    Sine wave amplitude-modulated by a ramp for transient simulation Locked

    15374 views
    2 replies
    Latest over 4 years ago
    by maaz2020
  • Discussion

    Default Find Filter Settings Locked

    10935 views
    1 reply
    Latest over 4 years ago
    by Dale Peterson
  • Discussion

    psd graph Locked

    10602 views
    0 replies
    Started over 4 years ago
    by abdurrahman0234
  • Discussion

    Accessing form fields names and values Locked

    11718 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    Adding fields to form programmatically Locked

    12331 views
    4 replies
    Latest over 4 years ago
    by dragank
  • Discussion

    Swap Activity Warning: Excessive swap activity Locked

    17474 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    How to detect some specific via that I'm not intended Locked

    625 views
    0 replies
    Started over 4 years ago
    by ichliebedich
  • Discussion

    How do people generate layer stack-up files for PCB manufacturer?

    17886 views
    5 replies
    Latest over 4 years ago
    by RFinley
  • Discussion

    Question about exporting simulation results to csv format, with ocean script Locked

    18655 views
    8 replies
    Latest over 4 years ago
    by dskang
  • Discussion

    Expand a Polygon along one dimension only with SKILL

    10720 views
    3 replies
    Latest over 4 years ago
    by markmalin
  • Discussion

    PCB and metal engraving - Help a young startup by answering a survey? Locked

    685 views
    0 replies
    Started over 4 years ago
    by fluidmetal
  • Discussion

    "A mandatory condition failed to be true, Condition: Snz_Nets::sxNetsNet"-error when running "timeDesign" in Innovus Locked

    3347 views
    2 replies
    Latest over 4 years ago
    by mbrand
  • Discussion

    FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit Locked

    14888 views
    2 replies
    Latest over 4 years ago
    by bikram94
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