Custom IC Design

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Discussion

Can't open cells in hierarchical schematic in Virtuoso

Category: Custom IC Design

By oAwad

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updated over 8 years ago by Andrew Beckett

1 replies • 3884 views
Discussion

layer map file for GDS transfer to virtuoso

Category: Custom IC Design

By oAwad

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updated over 8 years ago by oAwad

9 replies • 31953 views
Discussion

Sweeping 2 variables (at a time) in Parametric analysis

Category: Custom IC Design

By EngrZM

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updated over 8 years ago by Andrew Beckett

6 replies • 27470 views
Discussion

DEFT

Category: Custom IC Design

By samer1

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updated over 8 years ago by Andrew Beckett

3 replies • 14234 views
Discussion

Setting up a jitter simulation

Category: Custom IC Design

By itos

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updated over 8 years ago by Andrew Beckett

1 replies • 29938 views
Discussion

Performing Parasitic Extraction on a Layout which Contains an ADS Momentum Cell

Category: Custom IC Design

By canbaltaci

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updated over 8 years ago by Andrew Beckett

1 replies • 15631 views
Discussion

custom VCCS

Category: Custom IC Design

By Sali

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updated over 8 years ago by Andrew Beckett

4 replies • 16860 views
Discussion

Extracted simulation not working properly - netlist problem...?

Category: Custom IC Design

By cescoz

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updated over 8 years ago by Andrew Beckett

5 replies • 5415 views
Discussion

How to prevent automatically opening spectre.out in ViewFile-Window when running a simulation?

Category: Custom IC Design

By Magistus

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updated over 8 years ago by Magistus

2 replies • 14737 views
Discussion

viewing spectre simulation results right from the start

Category: Custom IC Design

By memphis

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updated over 8 years ago by memphis

3 replies • 16342 views
Discussion

Changing the I/O Type of a Pin in Layout View Using SKILL

Category: Custom IC Design

By canbaltaci

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updated over 8 years ago by canbaltaci

2 replies • 2798 views
Discussion

Problem in simulating SPICE model in spectre

Category: Custom IC Design

By farhan89

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updated over 8 years ago by Andrew Beckett

1 replies • 17101 views
Discussion

Cadence DRC Environment vars

Category: Custom IC Design

By samer1

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updated over 8 years ago by Andrew Beckett

1 replies • 15219 views
Discussion

Problem with simulating a PVS ERC spice netlist in spectre plus a skill for spice netlist reduction

Category: Custom IC Design

By RaghavasimhanT

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updated over 8 years ago by Andrew Beckett

2 replies • 15163 views
Discussion

ead_workshop - ade-xl error message (1921)

Category: Custom IC Design

By rafaelon

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updated over 8 years ago by Andrew Beckett

4 replies • 5319 views

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