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Custom IC Design

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  • Discussion

    [Solved] Unbound pins when running Assura LVS in Virtuoso Layout Suite L

    Category: Custom IC Design

    By dpalomeq

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    updated over 8 years ago by dpalomeq

    8 replies • 22369 views
  • Discussion

    ADE: Use of nested design variables in output expressions

    Category: Custom IC Design

    By sommer

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    updated over 8 years ago by Andrew Beckett

    3 replies • 17224 views
  • Discussion

    Access simulation data with OCEAN command getResult() / method description of classType famLeafAnalysis

    Category: Custom IC Design

    By sommer

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    started over 8 years ago

    0 replies • 13513 views
  • Discussion

    How to set different accuracy settings for different time periods in transient simulation.

    Category: Custom IC Design

    By vamshiky

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    updated over 8 years ago by Andrew Beckett

    6 replies • 25195 views
  • Discussion

    Corner Simulations of Multiple Test with dependent variables in ADE-XL

    Category: Custom IC Design

    By Skyler17

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    updated over 8 years ago by Andrew Beckett

    1 replies • 14594 views
  • Discussion

    parametrized netlist generation at scale

    Category: Custom IC Design

    By miwe

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    updated over 8 years ago by miwe

    4 replies • 16996 views
  • Discussion

    Only part of transient time displayed.

    Category: Custom IC Design

    By syafiq

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    updated over 8 years ago by syafiq

    1 replies • 13657 views
  • Discussion

    DC convergence problem

    Category: Custom IC Design

    By AmeliAmeli

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    updated over 8 years ago by Johanny Saenz

    2 replies • 22002 views
  • Discussion

    Manufacturing grid/ Routing grid

    Category: Custom IC Design

    By Cristina Ibane

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    updated over 8 years ago by Andrew Beckett

    3 replies • 16688 views
  • Discussion

    TO select all mosaics in visible area

    Category: Custom IC Design

    By Sampatcharu

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    updated over 8 years ago by Sampatcharu

    2 replies • 14110 views
  • Discussion

    integrate ansys Electromagnetic Suite 16 problem

    Category: Custom IC Design

    By rockyicer

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    updated over 8 years ago by Andrew Beckett

    7 replies • 18121 views
  • Discussion

    Regarding verilogA model of a discrete time delay free integrator

    Category: Custom IC Design

    By VivekNITg

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    updated over 8 years ago by Andrew Beckett

    1 replies • 17070 views
  • Discussion

    Relxpert prebert error

    Category: Custom IC Design

    By Amel

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    updated over 8 years ago by Andrew Beckett

    7 replies • 16817 views
  • Discussion

    transistor model - netlist - spectre - matlab

    Category: Custom IC Design

    By AmeliAmeli

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    updated over 8 years ago by Andrew Beckett

    1 replies • 1602 views
  • Discussion

    Noise sources in PSS analysis

    Category: Custom IC Design

    By OneNewBoy

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    updated over 8 years ago by Andrew Beckett

    3 replies • 15428 views
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