Custom IC Design

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ADE/ViVA Toggle Trace Visibility Bindkey

Category: Custom IC Design

By mconte

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updated over 12 years ago by mconte

2 replies • 1585 views
Discussion

how to list all devices and their operating region in a file

Category: Custom IC Design

By kxlux

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updated over 12 years ago by Andrew Beckett

1 replies • 15059 views
Discussion

Error in verilogA

Category: Custom IC Design

By sreeni

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updated over 12 years ago by sreeni

4 replies • 16708 views
Discussion

Cadence ADEXL: how to merge troubleshot point with rest of montecarlo data

Category: Custom IC Design

By spectrallypure

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updated over 12 years ago by Frank Wiedmann

12 replies • 20698 views
Discussion

skill to plot waveform contained in a file into w-viewer (could be VIVA)

Category: Custom IC Design

By azde

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updated over 12 years ago by Andrew Beckett

3 replies • 14632 views
Discussion

Is there a way to print model parameter using Hspice-D version2012.03 after running a simulation?

Category: Custom IC Design

By Alex Liao

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updated over 12 years ago by Andrew Beckett

9 replies • 20676 views
Discussion

STB analysis stops running ... with no error in output.log

Category: Custom IC Design

By Praveen K

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updated over 12 years ago by Praveen K

2 replies • 15406 views
Discussion

Ghost of Dragged object

Category: Custom IC Design

By Anonymous

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updated over 12 years ago by Anonymous

2 replies • 13912 views
Discussion

How to search for vias with rows or columsn property in layout XL

Category: Custom IC Design

By pham777

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updated over 12 years ago by pham777

6 replies • 15887 views
Discussion

operating points implementation (verilogA and CDF)

Category: Custom IC Design

By Fabb

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updated over 12 years ago by Andrew Beckett

3 replies • 14259 views
Discussion

importing EDIF file (library install)

Category: Custom IC Design

By oldnick

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updated over 12 years ago by oldnick

2 replies • 17655 views
Discussion

verilogin problem: modules are imported twice

Category: Custom IC Design

By Howel

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updated over 12 years ago by Howel

2 replies • 14727 views
Discussion

Virtuoso Strmout of selected cells

Category: Custom IC Design

By Stevemc12

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updated over 12 years ago by Andrew Beckett

3 replies • 15995 views
Discussion

ADE XL job dispatch behavior (LSF)

Category: Custom IC Design

By kentauta

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updated over 12 years ago by Andrew Beckett

1 replies • 15650 views
Discussion

Force ams netlister to skip ports/pins

Category: Custom IC Design

By Runner

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updated over 12 years ago by Andrew Beckett

1 replies • 1131 views

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