Custom IC Design

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Tip of the Week: Simplest ideal comparator

Category: Custom IC Design

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updated over 18 years ago by archive

2 replies • 22250 views
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Neocell setup wizard?

Category: Custom IC Design

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updated over 18 years ago by archive

6 replies • 16402 views
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Tip of the week: Rapidly save sets of simulation data

Category: Custom IC Design

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started over 19 years ago

0 replies • 13720 views
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Error while netlisting in UltrasimVerilog

Category: Custom IC Design

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started over 19 years ago

0 replies • 13417 views
Discussion

SDL flow crash in 6.1?

Category: Custom IC Design

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updated over 19 years ago by archive

1 replies • 14241 views
Discussion

Error while running PLL Top simulations with Ultrasim

Category: Custom IC Design

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updated over 19 years ago by archive

2 replies • 14333 views
Discussion

Diva drcAntenna cumulative check

Category: Custom IC Design

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updated over 19 years ago by archive

2 replies • 14206 views
Discussion

Beat frequency in SpectreRF PSS simulation

Category: Custom IC Design

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updated over 19 years ago by archive

2 replies • 22372 views
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neocell

Category: Custom IC Design

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updated over 19 years ago by archive

2 replies • 14447 views
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Using GTE in PAS 3.1 for generating PDKs?

Category: Custom IC Design

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started over 19 years ago

0 replies • 14948 views
Discussion

Impedance setting for ports in Spectre

Category: Custom IC Design

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updated over 19 years ago by archive

4 replies • 18415 views
Discussion

Cadence IC5.141 with NCSU design kit 1.2 or 1.5

Category: Custom IC Design

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updated over 19 years ago by archive

2 replies • 14565 views
Discussion

how does hiCreateInst work for pcells?

Category: Custom IC Design

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updated over 19 years ago by archive

5 replies • 15088 views
Discussion

leiHiCopy ?

Category: Custom IC Design

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updated over 19 years ago by archive

2 replies • 14029 views
Discussion

Error while extracting layout.

Category: Custom IC Design

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updated over 19 years ago by archive

5 replies • 15899 views

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