Custom IC Design

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Discussion

Skill Pcell "undefined function pow" at eval during LVS

Category: Custom IC Design

By AdrienL

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updated over 1 year ago by AdrienL

6 replies • 2399 views
Discussion

Virtuoso IC6.1.8-64b.500.31 Crashing

Category: Custom IC Design

By stefanwerleman

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started over 1 year ago

0 replies • 4377 views
Discussion

LVS Mismatch

Category: Custom IC Design

By Sazzad H

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updated over 1 year ago by RobMan

1 replies • 4790 views
Discussion

Is spc file available in ADE Explorer/Assembler?

Category: Custom IC Design

By mtzikara

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updated over 1 year ago by Andrew Beckett

1 replies • 803 views
Discussion

Transient Noise Analysis (fmin)

Category: Custom IC Design

By em1rk

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updated over 1 year ago by Andrew Beckett

3 replies • 6092 views
Discussion

Difference srrWave and drWave

Category: Custom IC Design

By tsnv

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updated over 1 year ago by Andrew Beckett

1 replies • 4535 views
Discussion

Refer to output expression by name, when name contains whitespaces and special characters

Category: Custom IC Design

By Volker T

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updated over 1 year ago by Volker T

2 replies • 4887 views
Discussion

VSR: How to avoid router to route over floating fill

Category: Custom IC Design

By MARTH0401

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updated over 1 year ago by RobMan

4 replies • 5076 views
Discussion

Plotting Template in ADE Assembler and ADE Explorer

Category: Custom IC Design

By IceTea

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started over 1 year ago

0 replies • 4117 views
Discussion

Transient Noise Simulation in Cadence Virtuoso

Category: Custom IC Design

By Maria98

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updated over 1 year ago by Andrew Beckett

2 replies • 5856 views
Discussion

How to inquire the discipline of a specific net in an AMS simulation via systemVerilog

Category: Custom IC Design

By Pedro P

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updated over 1 year ago by Andrew Beckett

1 replies • 4769 views
Discussion

Evaluated waveform discontinuity

Category: Custom IC Design

By sidm

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updated over 1 year ago by sidm

6 replies • 5748 views
Discussion

VSR not dropping vias to short all pins

Category: Custom IC Design

By MARTH0401

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updated over 1 year ago by RobMan

5 replies • 5466 views
Discussion

Maestro - custom window size for simulation log

Category: Custom IC Design

By firebolt3

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updated over 1 year ago by Andrew Beckett

4 replies • 1638 views
Discussion

Adapt .cal file to .rul file for PVS

Category: Custom IC Design

By Joan Serrano

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updated over 1 year ago by Joan Serrano

4 replies • 5423 views

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