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Custom IC Design

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  • Discussion

    Method to scale up or down lots of resistor/capacitor value together

    Category: Custom IC Design

    By FormerMember

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    updated over 5 years ago by henker

    1 replies • 2456 views
  • Discussion

    Mixed-signal CDL netlist export

    Category: Custom IC Design

    By Nicolas Callens

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 16115 views
  • Discussion

    LDO design and simulation

    Category: Custom IC Design

    By SHATADAL IIITG

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    •

    started over 5 years ago

    0 replies • 14670 views
  • Discussion

    Smooth dynamic parameter variation in transient sim

    Category: Custom IC Design

    By Quantum7

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 15929 views
  • Discussion

    Plotting temperature in a transient simulation

    Category: Custom IC Design

    By Quantum7

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    updated over 5 years ago by Quantum7

    9 replies • 21978 views
  • Discussion

    Pin placement does not show up

    Category: Custom IC Design

    By Nicolas Callens

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 14797 views
  • Discussion

    How to fix "*WARNING* file /home/Kaveri/CDS.log Malformed Lock-Stake file.", when running virtuoso?

    Category: Custom IC Design

    By Marben

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    updated over 5 years ago by Marben

    2 replies • 9956 views
  • Discussion

    Is CDL netlist *.PININFO pin1:O pin2:I pin3:IO property a syntax requirement?

    Category: Custom IC Design

    By max123321

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    updated over 5 years ago by Andrew Beckett

    3 replies • 3752 views
  • Discussion

    VerilogA

    Category: Custom IC Design

    By Suhas7

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 14657 views
  • Discussion

    spiceText view with AMS OSS netlister

    Category: Custom IC Design

    By RobinC

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    •

    updated over 5 years ago by Andrew Beckett

    3 replies • 15638 views
  • Discussion

    Input Capacitance Measurements of Digital Cells in Cadence Liberate

    Category: Custom IC Design

    By anurans

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    •

    updated over 5 years ago by anurans

    8 replies • 18562 views
  • Discussion

    Negative Power Numbers During the Synthesis Over a Custom Cell Library (Liberate)

    Category: Custom IC Design

    By anurans

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    •

    updated over 5 years ago by Guangjun Cao

    2 replies • 16700 views
  • Discussion

    I want a user manual for the switch in analoglib. where I can get this?

    Category: Custom IC Design

    By JAYDIP BISWAS

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 19594 views
  • Discussion

    path appearing different within IC616 and IC618

    Category: Custom IC Design

    By jaylin

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    •

    updated over 5 years ago by jaylin

    4 replies • 16055 views
  • Discussion

    sp1tswitch equivalent for pac simulations

    Category: Custom IC Design

    By nicodega

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    •

    updated over 5 years ago by Andrew Beckett

    6 replies • 16679 views
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