Custom IC Design

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Cadence Schematic - hotkey for hiding terminal & instance labels

Category: Custom IC Design

By firebolt

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updated over 3 years ago by firebolt

2 replies • 2895 views
Discussion

Different Monte Carlo Setups in the same run/run plan (Maestro)

Category: Custom IC Design

By jackrc11

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updated over 3 years ago by Andrew Beckett

3 replies • 4187 views
Discussion

psfascii format

Category: Custom IC Design

By shaarawy2023

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updated over 3 years ago by Andrew Beckett

1 replies • 9037 views
Discussion

Layout integration

Category: Custom IC Design

By Arashka

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updated over 3 years ago by iq79

1 replies • 8575 views
Discussion

tsmc65nm DFM_options

Category: Custom IC Design

By zaki177

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updated over 3 years ago by iq79

2 replies • 9381 views
Discussion

pss+pstb simulation of boost converter when it is unstable

Category: Custom IC Design

By midaslab

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updated over 3 years ago by Andrew Beckett

3 replies • 2629 views
Discussion

spectre netlist

Category: Custom IC Design

By shaarawy2023

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updated over 3 years ago by Andrew Beckett

1 replies • 9000 views
Discussion

How to split device fingers in Virtuoso MODGEN

Category: Custom IC Design

By Nader Fathy

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updated over 3 years ago by Nader Fathy

1 replies • 10200 views
Discussion

How to read in a text file separated by delays in Verilog A. They delays are relative and to be read from the text file?

Category: Custom IC Design

By Nisharg shah

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started over 3 years ago

0 replies • 8456 views
Discussion

Simple example/template for a (matrix based, if possible) schematic pcell

Category: Custom IC Design

By SteveVrk

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updated over 3 years ago by SteveVrk

3 replies • 2642 views
Discussion

Accessing analog voltages in hierarchy from Verilog AMS

Category: Custom IC Design

By amacSS

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updated over 3 years ago by amacSS

4 replies • 11115 views
Discussion

use of calcVal() to access expressions from other tests

Category: Custom IC Design

By AncisMichele

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updated over 3 years ago by AncisMichele

4 replies • 20721 views
Discussion

2x1 mux Shorted Internal Nets lvs error

Category: Custom IC Design

By ehdwns48

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started over 3 years ago

0 replies • 9061 views
Discussion

Netlister's subcircuit naming convention

Category: Custom IC Design

By ZoltanT

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updated over 3 years ago by lchensd

8 replies • 4797 views
Discussion

Drawing an Elongated Ellipse Shape

Category: Custom IC Design

By Ynishant

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updated over 3 years ago by Ynishant

2 replies • 9631 views

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