Custom IC Design

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ADE XL Timed Out Running Monte Carlo Simulation

Category: Custom IC Design

By spaceradlab

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updated over 8 years ago by Andrew Beckett

3 replies • 14926 views
Discussion

CDF instance information warning meaning

Category: Custom IC Design

By RVERP

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updated over 8 years ago by Andrew Beckett

1 replies • 14216 views
Discussion

When does opening an ADE-XL view cause also ViVa to open?

Category: Custom IC Design

By PatrikOsgnach

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updated over 8 years ago by PatrikOsgnach

4 replies • 14096 views
Discussion

Measurement of delay between change in value of two buses created using Analog to Digital function

Category: Custom IC Design

By prashantpd

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updated over 8 years ago by Andrew Beckett

1 replies • 14756 views
Discussion

gpdk045 vth at dcop is not same as model spec

Category: Custom IC Design

By rfham

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updated over 8 years ago by Andrew Beckett

2 replies • 14525 views
Discussion

how to use variable in parameter sweep

Category: Custom IC Design

By sjwprc

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updated over 8 years ago by Andrew Beckett

1 replies • 16562 views
Discussion

Monte Carlo: Define instance mismatch correlation in IC61.6/7

Category: Custom IC Design

By Majdo

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updated over 8 years ago by Andrew Beckett

1 replies • 2304 views
Discussion

multipart path - automatically fill path width with rows of subrectangles

Category: Custom IC Design

By caver456

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updated over 8 years ago by Andrew Beckett

1 replies • 651 views
Discussion

Transient Noise Simulation for Different input/output frequencies

Category: Custom IC Design

By EngrZM

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updated over 8 years ago by EngrZM

2 replies • 3485 views
Discussion

Copying A Maestro View and underlying schematics to a new library

Category: Custom IC Design

By Cra1g

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updated over 8 years ago by Cra1g

4 replies • 18628 views
Discussion

save DC operating points in ADEXL

Category: Custom IC Design

By SteveRFIC

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updated over 8 years ago by SteveRFIC

2 replies • 18568 views
Discussion

Variable instance number and bus width depending on CDF parameter

Category: Custom IC Design

By Johanny Saenz

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updated over 8 years ago by Andrew Beckett

1 replies • 15552 views
Discussion

PSTB loop-gain Phase-plot : error at lower frequency

Category: Custom IC Design

By jdp721

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updated over 8 years ago by jdp721

4 replies • 17545 views
Discussion

ADEXL: use DirectPlot->Main Form with saved data

Category: Custom IC Design

By Clidre

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updated over 8 years ago by Andrew Beckett

3 replies • 2006 views
Discussion

Rotate schematic component without rotating the component labels?

Category: Custom IC Design

By MatthewLove

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updated over 8 years ago by MatthewLove

2 replies • 15755 views

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