Custom IC Design

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Discussion

Multiple Via Cut Spacing for same ViaDefName

Category: Custom IC Design

By FormerMember

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started over 7 years ago

0 replies • 2232 views
Discussion

Auto routing constraints in cadence virtuoso

Category: Custom IC Design

By farhan89

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started over 7 years ago

0 replies • 14298 views
Discussion

probing signal in av_extracted_RC

Category: Custom IC Design

By HansB

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updated over 7 years ago by Quek

3 replies • 14047 views
Discussion

Multi-Voltage domain pin checks at schematic level

Category: Custom IC Design

By Johanny Saenz

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started over 7 years ago

0 replies • 13920 views
Discussion

Checking installation of PDK is correct

Category: Custom IC Design

By CxD7

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updated over 7 years ago by CxD7

2 replies • 17533 views
Discussion

CDF parameters reusing default value from veriloga

Category: Custom IC Design

By ernie123

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updated over 7 years ago by ernie123

2 replies • 15177 views
Discussion

APS: better Hyperthreading ON or OFF on the machine?

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

4 replies • 16331 views
Discussion

Library Manager: .cdsenv / .cdsinit settings not taking effect

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

4 replies • 25434 views
Discussion

design kits for a new member in cadence

Category: Custom IC Design

By tashtoush

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updated over 7 years ago by tashtoush

6 replies • 16729 views
Discussion

fail to use VAR as 'tran' analysis parameter

Category: Custom IC Design

By fatcat1206

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updated over 7 years ago by Andrew Beckett

3 replies • 4273 views
Discussion

How do you generate a layout from schematic in Virtuoso IC 6.1.5?

Category: Custom IC Design

By ernie123

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updated over 7 years ago by Andrew Beckett

3 replies • 20117 views
Discussion

how to enable to show all the simulation warnings

Category: Custom IC Design

By enzhu

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updated over 7 years ago by Andrew Beckett

1 replies • 15567 views
Discussion

Plotting across corners with internal sweep in maestro

Category: Custom IC Design

By Gabriel Puech

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updated over 7 years ago by Andrew Beckett

7 replies • 18545 views
Discussion

Custom digital placer can't use tap-cell

Category: Custom IC Design

By jsundermeyer

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updated over 7 years ago by Andrew Beckett

5 replies • 2180 views
Discussion

Export data to CSV format

Category: Custom IC Design

By CPete

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updated over 7 years ago by Andrew Beckett

21 replies • 61059 views

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