Custom IC Design

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Discussion

Layout Netlist and Topcell Netlist shows correct connections but LVS does not pass!!!

Category: Custom IC Design

By mehdina94rm

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updated over 8 years ago by mehdina94rm

2 replies • 18245 views
Discussion

Should I use the PIN or the NET layer for gnd?

Category: Custom IC Design

By dpalomeq

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updated over 8 years ago by dpalomeq

2 replies • 14453 views
Discussion

License server

Category: Custom IC Design

By Milt

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updated over 8 years ago by Marc Heise

1 replies • 14774 views
Discussion

Pins are not annotated using subcircuit (netlist)

Category: Custom IC Design

By Johanny Saenz

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updated over 8 years ago by Johanny Saenz

4 replies • 15976 views
Discussion

Measure DNL/INL in ADE-XL

Category: Custom IC Design

By migrg

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updated over 8 years ago by migrg

1 replies • 9120 views
Discussion

dft error with a valid transient waveform

Category: Custom IC Design

By Aldo2

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updated over 8 years ago by Aldo2

4 replies • 15336 views
Discussion

Problem in importing verilog netlist to cadence

Category: Custom IC Design

By Casp

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started over 8 years ago

0 replies • 14125 views
Discussion

Verilog-A, one time execution function

Category: Custom IC Design

By samer1

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updated over 8 years ago by samer1

6 replies • 21749 views
Discussion

scs files

Category: Custom IC Design

By samer1

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updated over 8 years ago by Quek

6 replies • 26955 views
Discussion

Exporting ADE-L Variables

Category: Custom IC Design

By netbug

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updated over 8 years ago by netbug

6 replies • 15372 views
Discussion

unwanted snapping in layout editor

Category: Custom IC Design

By huadel

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updated over 8 years ago by Andrew Beckett

1 replies • 16709 views
Discussion

Using DC operating point calculated from spectre in APS Simualtion over Corners

Category: Custom IC Design

By Johanny Saenz

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started over 8 years ago

0 replies • 13927 views
Discussion

What is license feature "Virtuoso_Spectre_GXL_MMSIM_Lk", and how to use it?

Category: Custom IC Design

By dontpanic

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updated over 8 years ago by dontpanic

2 replies • 4190 views
Discussion

stb and tran analysis discrepancy

Category: Custom IC Design

By FormerMember

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updated over 8 years ago by FormerMember

1 replies • 1544 views
Discussion

[Solved] Unbound pins when running Assura LVS in Virtuoso Layout Suite L

Category: Custom IC Design

By dpalomeq

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updated over 8 years ago by dpalomeq

8 replies • 22361 views

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