Custom IC Design

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Spectrum assistant for FFT - How is the signal freq decided?

Category: Custom IC Design

By jdp721

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updated over 8 years ago by Andrew Beckett

5 replies • 5069 views
Discussion

power drop not seen in av_extracted simulation

Category: Custom IC Design

By primemath

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updated over 8 years ago by Andrew Beckett

1 replies • 13564 views
Discussion

probe different point on power nets in av_extracted view

Category: Custom IC Design

By primemath

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updated over 8 years ago by primemath

2 replies • 14841 views
Discussion

"Report Parasitics" cannot be Clicked

Category: Custom IC Design

By canbaltaci

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updated over 8 years ago by canbaltaci

2 replies • 2133 views
Discussion

Generating a random signal in Virtuoso

Category: Custom IC Design

By Donatello

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updated over 8 years ago by vaity

2 replies • 17247 views
Discussion

LVS error while connecting bulk with source

Category: Custom IC Design

By saikatc

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started over 8 years ago

0 replies • 16239 views
Discussion

BSIM4 Model parameters significance

Category: Custom IC Design

By JagdishP

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updated over 8 years ago by Andrew Beckett

1 replies • 17907 views
Discussion

Insert a tangent line into a plot

Category: Custom IC Design

By CESA

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updated over 8 years ago by Andrew Beckett

13 replies • 24042 views
Discussion

Verilog Netlister compatible net-separator in OA ?

Category: Custom IC Design

By Emulator

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updated over 8 years ago by Emulator

10 replies • 17916 views
Discussion

Highlighting a group of nets which match a particular regular expression

Category: Custom IC Design

By debaabed

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updated over 8 years ago by debaabed

2 replies • 14085 views
Discussion

Virtuoso Schematic - Enviroment - "move/copy" Snap mode

Category: Custom IC Design

By Ionutz

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updated over 8 years ago by Ionutz

3 replies • 2764 views
Discussion

Cadence virtuoso tool related

Category: Custom IC Design

By salamkgp

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updated over 8 years ago by Andrew Beckett

3 replies • 18433 views
Discussion

QRC dbCreateNet/dbCreateTerm warnings?

Category: Custom IC Design

By drdanmc

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updated over 8 years ago by Andrew Beckett

1 replies • 1428 views
Discussion

Synchronous copy of group with MPP results in flattened MPP?

Category: Custom IC Design

By RVERP

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updated over 8 years ago by RVERP

4 replies • 16364 views
Discussion

SKILL: Print voltage to a text file in ADE XL over corners

Category: Custom IC Design

By Anonymous

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updated over 9 years ago by Anonymous

7 replies • 17431 views

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