Custom IC Design

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Discussion

PAC simulation issue, "No valid time points are specified"

Category: Custom IC Design

By venkmanbuster

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updated over 4 years ago by Andrew Beckett

4 replies • 2324 views
Discussion

LVS and QRC in higher hierarchical layout design level

Category: Custom IC Design

By Senan

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started over 4 years ago

0 replies • 10503 views
Discussion

Difference between "Extract Layout" and "Update" in Cadence Virtuoso Layout tools

Category: Custom IC Design

By Senan

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updated over 4 years ago by Senan

4 replies • 2569 views
Discussion

Extract Layout tool in Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 4 years ago by Senan

2 replies • 12572 views
Discussion

how to set env variable of probe option

Category: Custom IC Design

By sjwprcker

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updated over 4 years ago by sjwprcker

2 replies • 11096 views
Discussion

conflict between schematic_pin view and symbol view

Category: Custom IC Design

By sidm

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updated over 4 years ago by sidm

4 replies • 12450 views
Discussion

Ohm My God!

Category: Custom IC Design

By CADcasualty

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updated over 4 years ago by CADcasualty

4 replies • 12040 views
Discussion

sample count

Category: Custom IC Design

By abdurrahman0234

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updated over 4 years ago by abdurrahman0234

15 replies • 15767 views
Discussion

How to backannotate Monte-Carlo DCOP simulation results to schematic

Category: Custom IC Design

By eivan

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updated over 4 years ago by eivan

2 replies • 11502 views
Discussion

generating DC files for inter-dependent Tests in ADEXL

Category: Custom IC Design

By Niccolo Lacaita

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started over 4 years ago

0 replies • 10369 views
Discussion

problem with strobe period

Category: Custom IC Design

By Medya

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updated over 4 years ago by Andrew Beckett

5 replies • 21439 views
Discussion

convert selected signed out signal to unsigned

Category: Custom IC Design

By abdurrahman0234

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updated over 4 years ago by Andrew Beckett

1 replies • 11908 views
Discussion

ViVa is plotting old simulation result instead of the current simulation results

Category: Custom IC Design

By RFStuff

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updated over 4 years ago by JainN

4 replies • 12727 views
Discussion

2-stage CMOS OTA: LVS errors

Category: Custom IC Design

By Jose Sarmento

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updated over 4 years ago by Jose Sarmento

1 replies • 11354 views
Discussion

SOLVED - Problem to avoid the removal of some capacitors with low values with Spectre XPS tool while performing transient analysis

Category: Custom IC Design

By VitorLima

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updated over 4 years ago by MaximX

3 replies • 1891 views

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