Custom IC Design

Latest Posts

Discussion

PAC simulation issue, "No valid time points are specified"

Category: Custom IC Design

By venkmanbuster
•
updated over 4 years ago by Andrew Beckett

4 replies • 1980 views
Discussion

LVS and QRC in higher hierarchical layout design level

Category: Custom IC Design

By Senan
•
started over 4 years ago

0 replies • 9747 views
Discussion

Difference between "Extract Layout" and "Update" in Cadence Virtuoso Layout tools

Category: Custom IC Design

By Senan
•
updated over 4 years ago by Senan

4 replies • 2258 views
Discussion

Extract Layout tool in Cadence Virtuoso

Category: Custom IC Design

By Senan
•
updated over 4 years ago by Senan

2 replies • 11613 views
Discussion

how to set env variable of probe option

Category: Custom IC Design

By sjwprcker
•
updated over 4 years ago by sjwprcker

2 replies • 10267 views
Discussion

conflict between schematic_pin view and symbol view

Category: Custom IC Design

By sidm
•
updated over 4 years ago by sidm

4 replies • 11421 views
Discussion

Ohm My God!

Category: Custom IC Design

By CADcasualty
•
updated over 4 years ago by CADcasualty

4 replies • 10957 views
Discussion

sample count

Category: Custom IC Design

By abdurrahman0234
•
updated over 4 years ago by abdurrahman0234

15 replies • 14104 views
Discussion

How to backannotate Monte-Carlo DCOP simulation results to schematic

Category: Custom IC Design

By eivan
•
updated over 4 years ago by eivan

2 replies • 10669 views
Discussion

generating DC files for inter-dependent Tests in ADEXL

Category: Custom IC Design

By Niccolo Lacaita
•
started over 4 years ago

0 replies • 9592 views
Discussion

problem with strobe period

Category: Custom IC Design

By Medya
•
updated over 4 years ago by Andrew Beckett

5 replies • 20180 views
Discussion

convert selected signed out signal to unsigned

Category: Custom IC Design

By abdurrahman0234
•
updated over 4 years ago by Andrew Beckett

1 replies • 11004 views
Discussion

ViVa is plotting old simulation result instead of the current simulation results

Category: Custom IC Design

By RFStuff
•
updated over 4 years ago by JainN

4 replies • 11751 views
Discussion

2-stage CMOS OTA: LVS errors

Category: Custom IC Design

By Jose Sarmento
•
updated over 4 years ago by Jose Sarmento

1 replies • 10498 views
Discussion

SOLVED - Problem to avoid the removal of some capacitors with low values with Spectre XPS tool while performing transient analysis

Category: Custom IC Design

By VitorLima
•
updated over 4 years ago by MaximX

3 replies • 1596 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.