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Custom IC Design

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  • Discussion

    make smaller or hide overlay in Cadence Layout XL

    Category: Custom IC Design

    By hesaliveJim

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    updated over 4 years ago by Andrew Beckett

    1 replies • 11067 views
  • Discussion

    NPORT compression "not working"

    Category: Custom IC Design

    By TommasoF

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    updated over 4 years ago by TommasoF

    5 replies • 3194 views
  • Discussion

    Terminal is inherited in switch master XXX and not inherited in place master YYY

    Category: Custom IC Design

    By jjwikner

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    updated over 4 years ago by Andrew Beckett

    4 replies • 13596 views
  • Discussion

    Resistor Noise Calculation using FFT and Noise Analysis is different

    Category: Custom IC Design

    By Nader Fathy

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    updated over 4 years ago by FormerMember

    7 replies • 17366 views
  • Discussion

    Issues in accuracy of clock generation in Verilog-AMS with white noise jitter

    Category: Custom IC Design

    By RFStuff

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    updated over 4 years ago by RFStuff

    10 replies • 17729 views
  • Discussion

    How do I set transient strobeoutput to "all" in AMS simulation?

    Category: Custom IC Design

    By Nader Fathy

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    •

    updated over 4 years ago by Nader Fathy

    2 replies • 1803 views
  • Discussion

    How to plot the difference of simulation result from Monte carlo and standard simulation?

    Category: Custom IC Design

    By Martinsh

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    updated over 4 years ago by Andrew Beckett

    9 replies • 15231 views
  • Discussion

    VIVA zoom horizontal/vertical

    Category: Custom IC Design

    By amacSS

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    updated over 4 years ago by amacSS

    2 replies • 1857 views
  • Discussion

    Bad value "primary" for parameter - Characterising cells using Liberate

    Category: Custom IC Design

    By iamKarthikBK

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    started over 4 years ago

    0 replies • 1521 views
  • Discussion

    import a Spice Model in a schematic

    Category: Custom IC Design

    By Friedrich

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    updated over 4 years ago by Friedrich

    3 replies • 24393 views
  • Discussion

    Connecting PMOS body to VSS! in Layout XL

    Category: Custom IC Design

    By Demi

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    updated over 4 years ago by Quek

    1 replies • 20235 views
  • Discussion

    "the following branches form a loop of rigid branches"

    Category: Custom IC Design

    By Jose Sarmento

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    •

    updated over 4 years ago by Jose Sarmento

    2 replies • 3461 views
  • Discussion

    VerilogA $limit with spectre

    Category: Custom IC Design

    By camilloS

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    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 10921 views
  • Discussion

    Using variables with spectrumMeas

    Category: Custom IC Design

    By Rob Gregoire

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    •

    started over 4 years ago

    0 replies • 10426 views
  • Discussion

    Automatically Export Spectre AMS-Output-Data

    Category: Custom IC Design

    By FloPro

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    •

    updated over 4 years ago by FloPro

    2 replies • 11735 views
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