Custom IC Design

Latest Posts

Discussion

Batch export of parasitic values in nets

Category: Custom IC Design

By CSCNalu

$usertype
•
updated over 4 years ago by CSCNalu

2 replies • 12177 views
Discussion

scaling layout

Category: Custom IC Design

By MReza Mah

$usertype
•
updated over 4 years ago by Andrew Beckett

1 replies • 14320 views
Discussion

FreePDK45 usage in Virtuoso

Category: Custom IC Design

By kevin998x

$usertype
•
updated over 4 years ago by Andrew Beckett

10 replies • 25864 views
Discussion

use sweep and montecarlo at the same time

Category: Custom IC Design

By Went

$usertype
•
updated over 5 years ago by Andrew Beckett

3 replies • 12287 views
Discussion

Consistent path to results for corner simulation?

Category: Custom IC Design

By Mike Bichan

$usertype
•
updated over 5 years ago by Andrew Beckett

1 replies • 12645 views
Discussion

How can I place vias with the size exact same cut width without metals around?

Category: Custom IC Design

By BaaB

$usertype
•
updated over 5 years ago by Andrew Beckett

1 replies • 12212 views
Discussion

Cadence virtuoso CDB to OA conversion ( ERROR*loadcontext )

Category: Custom IC Design

By mirtaji65

$usertype
•
updated over 5 years ago by Andrew Beckett

6 replies • 6335 views
Discussion

How to use PSS to determine the output dynamic range ?

Category: Custom IC Design

By Young2020

$usertype
•
updated over 5 years ago by Frank Wiedmann

1 replies • 12320 views
Discussion

Variable Pnoise Stop Frequency

Category: Custom IC Design

By Conorp

$usertype
•
updated over 5 years ago by Frank Wiedmann

5 replies • 14950 views
Discussion

csh C script for automating the ocean simulation

Category: Custom IC Design

By Aksh

$usertype
•
updated over 5 years ago by FormerMember

14 replies • 17048 views
Discussion

How to change default schematic symbol colors

Category: Custom IC Design

By Sutlieff

$usertype
•
updated over 5 years ago by Andrew Beckett

1 replies • 14580 views
Discussion

Symbolic (Analytical) Transfer function from Cadence (XF/PZ) for Simulink modeling

Category: Custom IC Design

By willTspriggs

$usertype
•
updated over 5 years ago by willTspriggs

4 replies • 5717 views
Discussion

VCCAP Usage and Documentation

Category: Custom IC Design

By EEE student

$usertype
•
updated over 5 years ago by EEE student

18 replies • 24673 views
Discussion

Make layout more visible in layout L

Category: Custom IC Design

By BaaB

$usertype
•
updated over 5 years ago by Andrew Beckett

1 replies • 11830 views
Discussion

Can we use $table_model() in verilogAMS

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 5 years ago by Andrew Beckett

3 replies • 13196 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.