Custom IC Design

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Discussion

how to set flight line that is just indicating the connections about the node on schematic

Category: Custom IC Design

By ichiro

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updated over 3 years ago by Andrew Beckett

4 replies • 13976 views
Discussion

What is the Assembler equivalent of loading save output state in ADEXL?

Category: Custom IC Design

By BillH314

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updated over 3 years ago by BillH314

4 replies • 10942 views
Discussion

Strange sharp rise/fall in stb phase plot

Category: Custom IC Design

By SpiceMonkey

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updated over 3 years ago by SpiceMonkey

4 replies • 3068 views
Discussion

Saving more parameters of MOSFET during transient simulation

Category: Custom IC Design

By dragank

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updated over 3 years ago by dragank

2 replies • 11074 views
Discussion

Transient plot of broken asserts

Category: Custom IC Design

By dragank

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updated over 3 years ago by dragank

2 replies • 9375 views
Discussion

is it possible to pass integer to verilog-a module?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

2 replies • 11455 views
Discussion

Edge Triggered Current Source

Category: Custom IC Design

By Kevin Buck

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updated over 3 years ago by Kevin Buck

4 replies • 10812 views
Discussion

How cadence generate the "IP Design.XML" file?

Category: Custom IC Design

By huhushuai

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updated over 3 years ago by Andrew Beckett

1 replies • 1888 views
Discussion

speeding up .hb at a certain stage

Category: Custom IC Design

By FredWang

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updated over 3 years ago by FormerMember

6 replies • 11857 views
Discussion

Pin size on CMOS circuit layout design

Category: Custom IC Design

By Senan

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started over 3 years ago

0 replies • 9305 views
Discussion

IC 6.1.7 on RHEL8

Category: Custom IC Design

By ddelrio

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updated over 3 years ago by ddelrio

2 replies • 13464 views
Discussion

About Multi technology simulation

Category: Custom IC Design

By ichiro

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updated over 3 years ago by ichiro

2 replies • 10193 views
Discussion

How to embed waveform setup (.grf) in maestro views? (or: how to propagate .grf files along with their associated cells?)

Category: Custom IC Design

By dontpanic

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updated over 3 years ago by dontpanic

2 replies • 9954 views
Discussion

How to report running time of simulation in adexl?

Category: Custom IC Design

By Holz

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updated over 3 years ago by Holz

1 replies • 9187 views
Discussion

Pspice model of memrister running in Virtuoso

Category: Custom IC Design

By Ranjan Yadav

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updated over 3 years ago by Ranjan Yadav

6 replies • 14003 views

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